• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.520-521
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• 2017

The converted error is occurred by the time difference between the time interval signal and the clock in a Time-to-Digital Converter of counter-type. If the clock period is $T_{CLOCK}$ the converted error is a maximum $T_{CLOCK}$ by the time difference between the start signal and the clock. And the converted error is a maximum $-T_{CLOCK}$ by the time difference between the stop signal and the clock. However, when the clock is synchronized with the start signal and the colck is generated during the time interval signal the range of converted digital error is from 0 to $(1/2)T_{CLOCK}$.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.25 no.6_1
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• pp.537-543
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• 2007

Since the GPS absolute positioning with pseudorange measurements can significantly be affected by the observation error, the time series analysis of the GPS receiver clock errors was performed in this study. From the estimated receiver clock errors, the time series model is generated, and constrained back in the absolute positioning process. One of the CORS (Continuously Operating Reference Stations) network is used to analyze the behavior of the receiver clock. The dominant part of the model is the linear trend during 24 hours, and the seasonal component is also estimated. After constraining the modeled receiver clock errors, the estimated position error compared to the published coordinates is improved from ${\pm}11.4\;m\;to\;{\pm}9.5\;m$ in 3D RMS.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.3
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• pp.439-445
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• 2001

In this paper, we propose a method that can minimize time-error when a commercial rubidium atomic clock is used as a portable reference clock. A linear interpolation method which was widely used is not based upon long-term stability, but our new method is considered to reduce time error. The comparison results between two method have shown that time error of our new approach considering with long-term stability is better than that of linear interpolation method within observation duration about one and half days. In addition, when the role of a rubidium atomic clock as a portable reference clock is completed within 12 hours, our new method can provide at most maximum time-error of 10 ns which is shorter than 15 ns in conventional method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.3
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• pp.225-231
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• 2011

The satellite clock anomalies, one of the abnormal signal factors of the GPS satellites, can have a significant impact on the GPS measurements. However, it can be difficult to detect the anomalies of the satellites clock before the range of the satellites clock error becomes bigger than the range of the other factors, due to the measurement including error of the orbit, ionosphere delay, troposphere delay, multipath and receiver clock. In order to perform quick and accurate detection by minimization of critical range in anomalies of the satellites clock, this paper suggested a solution to detect precise anomalies of the satellites clock after application of carrier smoothing filter from measurement by dual-frequency and adjustment of errors which can be occurred by other factor and the receiver clock errors. The performance of the proposed method was confirmed by comparing to the satellite clock biases which are provided by IGS.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.36 no.6
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• pp.621-628
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• 2018

More than four visible GPS (Global Positioning System) satellites are required to obtain absolute positioning. However, it is not easy to satisfy this condition when a rover is in such unfavorable condition as an urban area. As a consequence, clock-aided positioning has been used as an alternative method especially when the number of visible satellites is three providing that receive clock error information is available. In this study, LSC (Least-Squares Collocation) method is proposed to interpolate clock errors for clock-aided positioning after analyzing the characteristics of receiver clock errors. Numerical tests are performed by using GPS data collected at one of Korean CORS (Continuously Operating Reference Station) and a nearby GPS station. The receiver clock errors are obtained through the DGPS (Differential GPS) positioning technique and segmentation procedures are applied for efficient interpolation. Then, LSC is applied to predicted clock error at epoch which clock information is not available. The numerical test results are analyzed by examining the differences between the original and interpolated clock errors. The mean and standard deviation of the residuals are 0.24m and 0.49m, respectively. Therefore, it can be concluded that sufficient accuracy can be obtained by using the proposed method in this study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.5
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• pp.893-898
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• 2017

A TDC(Time-to-Digital Converter) of counter-type is designed by $0.18{\mu}mCMOS$process and the supply voltage is 1.5 volts. The converted error of maximum $T_{CK}$ is occurred by the time difference between the start signal and the clock when the period of clock is $T_{CK}$ in the conventional TDC. And the converted error of -$T_{CK}$ is occurred by the time difference between the stop signal and the clock. However in order to compensate the disadvantage of the conventional TDC the clock is generated within the TDC circuit and the clock is synchronized with the start and stop signals. In the designed TDC circuit the conversion error is not occurred by the difference between the start signal and the click and the magnitude of conversion error is reduced (1/2)$T_{CK}$ by the time difference between the stop signal and the clock.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.394-397
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• 2003

In this paper, we have proposed a clock recovery algorithm of OFDM/QPSK-DMR(Orthogonal Frequency Division Multiplexing/Quadrature Phase Shift Keying Modulation-Digital Microwave Radio)system using BL-PSF(Band Limited-Pulse Shaping Filter) and have analyzed the clock phase error variance performance of OFDM/QPSK and single carrier DMR systems. The existing OFDM/QPSK-DMR system using the windowing requires training sequence or CP(Cyclic Prefix) to synchronize a receiver clock frequency Because there is no training sequence or CP(Cyclic prefix) in our proposed DMR system, the proposed clock recovery algorithm is useful to the OFDM/QPSK-DMR system using BL-PSF, The simulation results confirm that the proposed clock recovery algorithm has the same clock phase error variance performance in a single carrier DMR system under AWGN(Additive White Gaussian Noise) environment.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.429-436
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• 2014

This paper proposes three methods of the time synchronization for Pseudolite and GPS and analyzes pseudolite time synchronization error factors for software based performance evaluation on proposed time synchronization methods. Proposed three time synchronization methods are pseudolite time synchronization station construction method, method by using UTC(KRIS) clock source and GPS timing receiver based time synchronization method. Also, we analyze pseudolite time synchronization error factors such as errors of pseudolite clock and reference clock, time delay as clock transmission line, measurement error of time interval counter and error as clock synchronization algorithm to design simulation platform for performance evaluation of pseudolite time synchronization.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.309-314
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• 2006

In general DGPS system, the correction message is transferred to users by wireless modem. To cover wide area, many DGPS station should be needed. And DGPS users must have a wireless modem that is not necessary in standalone GPS. But SBAS users don't need a wireless modem to receive DGPS corrections because SBAS correction message is transmitted from the GEO satellite by L1 frequency band. SBAS signal is generated in the GUS(Geo Uplink Subsystem) and uplink to the GEO satellite. This uplink transmission process causes two problems that are not existed in GPS. The one is a time delay in the uplink signal. The other is an ionospheric problem on uplink signal, code delay and carrier phase advance. These two problems cause ranging error to user. Another critical ranging error factor is clock synchronization. SBAS reference clock must be synchronized with GPS clock for an accurate ranging service. The time delay can be removed by close loop control. We propose uplink ionospheric error correcting algorithm for C/A code and carrier. As a result, the ranging accuracy increased high. To synchronize SBAS reference clock with GPS clock, I reviewed synchronization algorithm. And I modified it because the algorithm didn't consider doppler that caused by satellites' dynamics. SBAS reference clock synchronized with GPS clock in high accuracy by modified algorithm. We think that this paper will contribute to basic research for constructing satellite based DGPS system.