• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.40-47
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• 2009

This paper presents new drain bias scheme for the linearity enhancement of envelope tacking power amplifiers for W-CDMA base-stations. In the conventional envelope tracking power amplifiers, the drain bias voltage is lowered close to the knee voltage of transistor, resulting in the severe linearity degradation. To solve this problem, it is proposed in this paper that the amplifier is biased in the conventional class AB mode with a fixed drain bias voltage if the input envelope is low and in the envelope tracking mode otherwise. Moreover, the drain bias in the envelope tracking mode is newly determined to minimized the distortion. To verify the effectiveness of the proposed bias scheme, simulation is performed on the W-CDMA based-station envelope tracking power amplifier using class AB Si-LDMOS power amplifier. It is shown from the simulation that the proposed bias scheme allows a drastic linearity enhancement with the comparable efficiency enough to meet the requirement of W-CDMA base-station without additional linearization techniques.

• ETRI Journal
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• v.35 no.2
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• pp.226-233
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• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.276-282
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• 2015

Until recently, power amplifiers using LDMOS were Class-AB and Doherty type, and showed 55 % efficiency for narrowband of 60 MHz bandwidth. However, owing to the RRH application of base stations power amplifier module, a bandwidth expansion of at least 100 MHz and high efficiency power amplifiers of at least 60 % power efficiency are required. In this study, a Class-J power amplifier was designed by optimizing an output matching circuit so that the second harmonic load will contain a pure reactance element only and have broadband characteristics by using GaN HEMT. The measurements showed that a 45 W Class-J power amplifier with a power added efficiency of 60~75 % was achieved when continuous wave signals were input at 1.6~2.3 GHz, including W-CDMA application.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.2
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• pp.249-258
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• 1998

In land mobile communication, very extensive studies on pilot symbol assisted modulation (PSAM) have been made on fading compensation. This paper analyzes the effect of power amplifier nonlinearity on PSA-QAM with maximal ratio combining space diversity. In practical PSAM, information on fading is obtained through interpolation of the pilot symbols. We employed the interpolation filter which could minimize the average power of error and analyzed effects on the system performance of the number of filter taps, period of the pilot symbol frame, and the Doppler frequency. Nonlinear power amplifiers of class AB, B, and C were incorporated in the system models and their AM/AM and AM/PM characteristics were taken into account in the performance analysis. We showed the performance variations according to the types of the nonlinear power amplifiers in the AWGN and Rayleigh fading channels using nonlinear compensation technique, Cartesian Feedback Loop (CFB).

• ETRI Journal
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• v.39 no.1
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• pp.51-61
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• 2017

This paper demonstrates a systematic approach for the design of broadband, high efficiency, high power, Class-AB RF amplifiers with high gain flatness. It is usually difficult to simultaneously achieve a high gain flatness and high efficiency in a broadband RF power amplifier, especially in a high power design. As a result, the use of a computer-aided simulation is most often the best way to achieve these goals; however, an appropriate initial value and a systematic approach are necessary for the simulation results to rapidly converge. These objectives can be accomplished with a minimum of trial and error through the following techniques. First, signal gain variations are reduced over a wide bandwidth using a proper pre-matching network. Then, the source and load impedances are satisfactorily obtained from small-signal and load-pull simulations, respectively. Finally, two high-order Chebyshev low-pass filters are employed to provide optimum input and output impedance matching networks over a bandwidth of 100 MHz-500 MHz. By using an EM simulation for the substrate, the simulation results were observed to be in close agreement with the measured results.

• Journal of Advanced Navigation Technology
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• v.21 no.1
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• pp.66-71
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• 2017

This paper describes implementation of a 165 MHz, 5 kW RF high power amplifier (HPA) for particle accelerator applications. The HPA consists of a drive amplifier for main amplifiers driving, sixteen 600 W class-AB push-pull power amplifier pallets and Wilkinson power divider/combiner using lumped LC components, which are divided/combined power amplifier pallet outputs. To detected the amplifier circuit of normal and reflected output power conditions, we used a bidirectional coupler. To radiate heat of main power amplifier, we were used an water-cooled copper plates to go through a water for radiation of heat. The HPA of center frequency 165 MHz has archived an efficiency of 62.5 % at 5 kW of power level experimentally.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.47-55
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• 1996

An optical transmitter, which is a key component of the optical transmission system, converts the electrical signal to optical signal and consists of a high-speed current-pulse driver for laser diode and low-speed feedback loops that stabilize optical power against aging, power supply voltage fluctuations, and ambient temperature changes. In this paper, the power-stabilizing part, which forms the bulk of the optical transmitter circuitry was designed in integrted circuits. Operational amplifiers and reference voltage generation circuits, which were identified as key building blocks for the power-stabilizing feedback loops, were designed and were subsequently verified through HSPICE simulations. The designed operational amplifier consists of a two-stage folded cascode amplifier and class AB output stage, whereas the reference voltage is obtained by bandgap reference circuits. Finally the power-stabilizing circuitry was laid out based on 3\mu$m CMOS design rules for fabrication.

• Journal of electromagnetic engineering and science
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• v.14 no.4
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• pp.376-381
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• 2014

We present a CMOS rail-to-rail class-AB amplifier using dynamic current biasing to improve the delay response of the error amplifier in a low-dropout (LDO) regulator, which is a building block for a wireless power transfer receiver. The response time of conventional error amplifiers deteriorates by slewing due to parasitic capacitance generated at the pass transistor of the LDO regulator. To enhance slewing, an error amplifier with dynamic current biasing was devised. The LDO regulator with the proposed error amplifier was fabricated in a $0.35-{\mu}m$ high-voltage BCDMOS process. We obtained an output voltage of 4 V with a range of input voltages between 4.7 V and 7 V and an output current of up to 212 mA. The settling time during line transient was measured as $9{\mu}s$ for an input variation of 4.7-6 V. In addition, an output capacitor of 100 pF was realized on chip integration.

• Journal of electromagnetic engineering and science
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• v.11 no.1
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• pp.16-26
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• 2011

This paper presents high power and high efficiency Doherty amplifiers for 2.345 GHz wireless broadband (WiBro) applications that use a Nitronex 125-W ($P_{3dB}$) GaN high electron mobility transistor (HEMT). Two- and three-way Doherty amplifiers and a saturated Doherty amplifier using Class-F circuitry are implemented. The measured result for a center frequency of 2.345 GHz shows that the two-way Doherty amplifier attains a high $P_{3dB}$ of 51.5 dBm, a gain of 12.5 dB, and a power-added efficiency (PAE) improvement of about 16 % compared to a single class AB amplifier at 6-dB back-off power region from $P_{3dB}$. For a WiBro OFDMA signal, the Doherty amplifier provides an adjacent channel leakage ratio (ACLR) at 4.77 MHz offset that is -33 dBc at an output power of 42 dBm, which is a 9.5 dB back-off power region from $P_{3dB}$. By employing a digital pre-distortion (DPD) technique, the ACLR of the Doherty amplifier is improved from -33 dBc to -48 dBc. The measured result for the same frequency shows that the three-way Doherty amplifier, which has a $P_{3dB}$ of 53.16 dBm and a gain of 10.3 dB, and the saturated Doherty amplifier, which has a $P_{3dB}$ of 51.1 dBm and a gain of 10.3 dB, provide a PAE improvement of 11 % at the 9-dB back-off power region and 7.5 % at the 6-dB back-off region, respectively, compared to the two-way Doherty amplifier.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.43-51
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• 2013

This paper presents a design and implementation of a low power switched-capacitor 3rd-order delta-sigma modulator for a digital hearing-aid application. The power consumption is reduced by minimizing the output swing of integrators through optimizing the coefficients of modulator architecture and using class-AB output operational amplifiers. The modulator was implemented in a 130nm CMOS technology, and measured to have 79dB of SNR(Signal-to-Noise Ratio) in the signal bandwidth between 100Hz and 10kHz with an oversampling ratio of 160. The power consumption was $60{\mu}W$ from 1.2V power supply and the modulator core occupied $0.53mm{\times}0.53mm$.