• Journal of the Institute of Electronics Engineers of Korea SD
• /
• 제39권11호
• /
• pp.24-32
• /
• 2002

In this paper we implemented various image processing filtering using the format converter. This design method is based on realized the large processor-per-pixel array by integrated circuit technology. These two types of integrated structure are can be classify associative parallel processor and parallel process DRAM(or SRAM) cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilize the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start. As a result, we obtained three result that 1)simple smoothing suppresses higher spatial frequencies, reducing noise but also blurring edges, 2) a smoothing and segmentation process reduces noise while preserving sharp edges, and 3) median filtering, like smoothing and segmentation, may be applied to reduce image noise. Median filtering eliminates spikes while maintaining sharp edges and preserving monotonic variations in pixel values.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• 제37권5호
• /
• pp.55-65
• /
• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• 제16권12호
• /
• pp.1336-1347
• /
• 1991

In this paper, The PC interface for packet terminal of ISDN is designed and implemented in order to build packet communication networks which share computer resources and exchange informations between computer in the ISDN environment. The PC interface for packet terminal of ISDN constitutes S interface handler part which controls functions of ISDN layer1 and layer 2, constitutes packet handler part which controls services of X.25 protocol in the packet level.Where, The function of ISDN layer1 provides rules of electrical and mechanical characteristics, services for ISDN layer 2. The function of ISDN layer 2 provides function of LAPD procedure, services for X.25 The X.25 specifies interface between DCE and DTE for terminals operrating in the packet mode. The S interface handler part is orfanized by Am 79C30 ICs manufactured by Advanecd Micro Devices. ISDN packet handler part is organiged by AmZ8038 for FIFO for the purpose of D channel. The common signal procedure for D channel is controlled by Intel's 8086 microprocessor. The S interface handler part is based on ISDN layer1,2 is controlled by mail box in order to communicate between layers. The ISDN packet handler part is based on module in the X.25 lebel. The communication between S interface handler part and ISDN packet handler part is organized by interface controller.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• 제11권11호
• /
• pp.4360-4366
• /
• 2010

It is impossible for all athletes to be satisfied with a single training program due to the fact that they have different physiological characteristics and needs. However, paucity studies have been introduced a specific training program for high school sprinters. Therefore, this study was designed to help develop and introduce the training program with a physical examination to enhance sprinting performance for experienced high school sprinters. VO2max, muscular strength, basic physical ability, and body composition were measured before and after a 24 week training program. The following are the conclusions based on the results of this study: 1) body fat percentage was increased after 24 weeks of training. Fat free mass and the amount of water in the body increased by 1.5% and 1.1% respectively, 2) $VO_2$maxand anaerobic threshold level showed a significant increase after 24 weeks of training, 3) exercise duration and anaerobic threshold duration were also increased after 24 weeks of training, but not statistically significant, and 4) muscular strength significantly increased due to the execution of combined weight training and circuit training. Development and implementation of the training program in this study made sprinters' physical capacities better in VO2max, anaerobic threshold, and muscular strength and body composition. Also, sprinters were able to increase fat free mass through 24 weeks of training due to increased muscle mass. Therefore, a training program for high school sprinters should include a physical examination to enhance sprinting performance and prevent sports injuries.

• Journal of Practical Engineering Education
• /
• 제10권1호
• /
• pp.17-24
• /
• 2018

Through the design and production of works for the third semester as a major unit, It is proposed the process of satisfying the graduation standards with the design and production process of the drone which can be applied to various mobile environments. Using the shape of Ring Propeller, it is made to be able to play both the role of generating lift as a propeller and the role of a wheel that touches the ground through the surface of the rim. In addition, the Servo Motor is used to convert the drive shaft of the motor to the correct angle according to the command. Then, based on the idea, the 3D printing is implemented to confirm the result of the configuration, and the circuit for driving the propulsion is designed and manufactured. As a result, the conversion of the desired propulsion system during air navigation and operation failed due to the weight increase of the propellant. It is confirmed that the size of the thrust and the tolerance limit of the ring propeller are the errors. Through these processes, it has been recognized to have experience of creative thinking and cooperation through engineering approach and comprehensive design, and confirmed to satisfy the graduation criteria by writing an engineering paper on the result.

• Journal of the Korean Electrochemical Society
• /
• 제22권2호
• /
• pp.69-78
• /
• 2019

Lithium metal anode with the highest theoretical capacity to replace graphite anodes are being reviewed. However, the dendrite growth during repeated oxidation/reduction reaction on lithium metal surface, which results in poor cycle performance and safety issue has hindered its successful implementation. In our previous work, we solved this problem by using surface modification technique whereby a surface pattern on lithium metal anode is introduced. Although the micro-patterned Lithium metal electrode is beneficial to control Li metal deposition efficiently, it is difficult to control the mossy-like Li granulation at high current density ($>2.0mA\;cm^{-2}$). In this study, we introduce vinylene carbonate (VC) electrolyte additive on micro patterned lithium metal anode to suppress the lithium dendrite growth. Owing to the synergetic effect of micro-patterned lithium metal anode and VC electrolyte additive, lithium dendrite at a high current density is dense. As a result, we confirmed that the cycle performance was further improved about 6 times as compared with the reference electrode.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• 제11권3호
• /
• pp.23-32
• /
• 2001

Since the LILI-128 cipher is a clock-controlled keystream generator, the speed of the keystream data is degraded in a clock-synchronized hardware logic design. Basically, the clock-controlled $LFSR_d$ in the LILI-128 cipher requires a system clock that is 1 ~4 times higher. Therefore, if the same clock is selected, the system throughput of the data rate will be lowered. Accordingly, this paper proposes a 4-bit parallel $LFSR_d$, where each register bit includes four variable data routines for feed feedback of shifting within the $LFSR_d$ . Furthermore, the timing of the propose design is simulated using a $Max^+$plus II from the ALTERA Co., the logic circuit is implemented for an FPGA device (EPF10K20RC240-3), and the throughput stability is analyzed up to a late of 50 Mbps with a 50MHz system clock. (That is higher than the 73 late at 45 Mbps, plus the maximum delay routine in the proposed design was below 20ns.) Finally, we translate/simulate our FPGA/VHDL design to the Lucent ASIC device( LV160C, 0.13 $\mu\textrm{m}$ CMOS & 1.5v technology), and it could achieve a throughput of about 500 Mbps with a 0.13$\mu\textrm{m}$ semiconductor for the maximum path delay below 1.8ns.

• Journal of the Korea Society of Computer and Information
• /
• 제27권2호
• /
• pp.153-161
• /
• 2022

Physical activities are decreasing and sitting time is increasing due to the automation, smartization, and intelligence of necessary household items throughout daily life. Recent healthcare studies have reported that the likelihood of obesity, diabetes, cardiovascular disease, and early death increases in proportion to sitting time. In this paper, we develop a sitting posture correction cushion in real time using capacitive pressure sensor based on conductive textile. It develops a pressure sensor using conductive textile, a key component of the posture correction cushion, and develops a low power-based pressure measurement circuit. It provides a function to transmit sensor values measured in real time to smartphones using BLE short-range wireless communication on the posture correction cushion, and develops a mobile application to check the condition of the sitting posture through these sensor values. In the mobile app, you can visualize your sitting posture and check it in real time, and if you keep it in the wrong posture for a certain period of time, you can notify it through an alarm. In addition, it is possible to visualize the sitting time and posture accuracy in a graph. Through the correction cushion in this paper, we experiment with how effective it is to correct the user's posture by recognizing the user's sitting posture, and present differentiation and excellence compared to other product.

• Journal of Internet of Things and Convergence
• /
• 제9권6호
• /
• pp.93-98
• /
• 2023

In paddy rice farming, water management is a critical task. To suppress weed emergence during the early stages of growth, fields are deeply flooded, and after transplantation, the water level is reduced to promote rooting and stimulate stem generation. Later, water is drained to prevent the production of sterile tillers. The adequacy of water supply is influenced by various factors such as field location, irrigation channels, soil conditions, and weather, requiring farmers to frequently check water levels and control the ingress and egress of water. This effort increases if the fields are scattered in remote locations. Automated irrigation systems have been considered to reduce labor and improve productivity. However, the net income from rice production in 2022 was about KRW 320,000/10a on average, making it financially unfeasible to implement high-cost devices or construct new infrastructure. This study focused on developing an IoT-Based irrigation valve that can be easily integrated into existing agricultural infrastructure without additional construction. The research was carried out in three main areas: Firstly, an irrigation valve was designed for quick and easy installation on existing agricultural pipes. Secondly, a power circuit was developed to connect a low-power Cat M1 communication modem with an Arduino Nano board for remote operation. Thirdly, a cloud-based platform was used to set up a server and database environment and create a web interface that users can easily access.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• 제27권12C호
• /
• pp.1288-1298
• /
• 2002

To implement elliptic curve cryptosystem in GF(2$\^$m/) at high speed, a fast divider is required. Although bit-parallel architecture is well suited for high speed division operations, elliptic curve cryptosystem requires large m(at least 163) to support a sufficient security. In other words, since the bit-parallel architecture has an area complexity of 0(m$\^$m/), it is not suited for this application. In this paper, we propose a new serial-in serial-out systolic array for computing division operations in GF(2$\^$m/) using the standard basis representation. Based on a modified version of tile binary extended greatest common divisor algorithm, we obtain a new data dependence graph and design an efficient bit-serial systolic divider. The proposed divider has 0(m) time complexity and 0(m) area complexity. If input data come in continuously, the proposed divider can produce division results at a rate of one per m clock cycles, after an initial delay of 5m-2 cycles. Analysis shows that the proposed divider provides a significant reduction in both chip area and computational delay time compared to previously proposed systolic dividers with the same I/O format. Since the proposed divider can perform division operations at high speed with the reduced chip area, it is well suited for division circuit of elliptic curve cryptosystem. Furthermore, since the proposed architecture does not restrict the choice of irreducible polynomial, and has a unidirectional data flow and regularity, it provides a high flexibility and scalability with respect to the field size m.