• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.3
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• pp.16-23
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• 1998

In this paper, we present a fast and efficient Iterative Improvement Partitioning(IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. The IIP algorithms are very widely used in VLSI circuit partition due to their time efficiency. As the performance of these algorithms depends on choices of moving cell, various methods have been proposed. Specially, Cluster-Removal algorithm by S. Dutt significantly improved partition quality. We indicate the weakness of previous algorithms wjere they used a uniform method for choice of cells during for choice of cells during the improvement. To solve the problem, we propose a new IIP technique that selects the method for choice of cells according to the improvement status and present hybrid bucket structures for easy implementation. The time complexity of proposed algorithm is the same with FM method and the experimental results on ACM/SIGDA benchmark circuits show improvment up to 33-44%, 45%-50% and 10-12% in cutsize over FM, LA-3 and CLIP respectively. Also with less CUP tiem, it outperforms Paraboli and MELO represented constructive-partition methods by about 12% and 24%, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.62-71
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• 1994

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

• Journal of the Korea Safety Management & Science
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• v.16 no.2
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• pp.111-119
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• 2014

This paper describes the design and implementation of a electromagnetic energy harvesting mechanism and electronic circuit for autonomous emergency call system. This analysis results show the power output of the proposed harvesting mechanism and circuit up to max power output 5V and it can hold up to 65 msec of the power generation and 10msec of the RF transmission. Based on the these testing results, the implementation of autonomous emergency call device without battery power or any external power source is feasible.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.2
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• pp.319-324
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• 1996

Using random pulse stream, a number can be transformed to the pulse stream with the probability value. So the digital value are computed by simple digital gates. Thus it will be possible to build a small and strong noise immunity processing element. We propose a faster convergence algorithm using a new methods for better performance of Random Number Generator(RNG) an the nonlinear transfer function(Sigmoid function)in this paper. And a feedback circuit were fitted for pulse stream in this paper. We proposed method is simulated with C program language and conformed by circuit implementation. Finally a system for hand written number recognition is constructed by FPGA and its performance verified.

• Journal of the Institute of Convergence Signal Processing
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• v.3 no.1
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• pp.87-92
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• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a stochastic evolution algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• Journal of the Korea Society of Computer and Information
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• v.7 no.3
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• pp.42-48
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• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.10
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• pp.27-34
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• 1993

In this paper, a driver system is designed and implemented to achieve 4-level gray scale CH TFEL(Thin Film ElectroLuminescent) flat panel display. To implement the driver system, commercial EL driver IC chips are used to apply high voltage pulses to the EL panel and a high voltage switching circuit is designed for the EL driver IC. A new method of reducing storage delay time of transistor is proposed to obtain a reliable switching circuit. The controller for EL driver and switching circuit is also designed. The designed driving scheme applicable to EL display with 4-level gray scale is based on the linear characteristics of brightness vs. frequency of AC TFEL. By experiment, it has been shown that the brightness of AC TEFL display with the implemented driving system is controlled by the level of gray scale.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.8 no.3
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• pp.152-156
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• 2009

This paper designs and implements wake up module for WBAN/USN sensor node which is using dynamic reference voltage demodulation circuit. When a comparator is used in a system for detecting received voltage level, comparator must have a reference voltage. However, the reference voltage is fixed, the system can communicate only a few range because received voltage level is changing widely due to distance of the wireless sensor nodes. Therefore, the proposed wake up module employs a dynamic reference voltage demodulation circuit for increasing communication range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.115-121
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• 2004

GenJTAG implemented in this paper is an automatic web-based boundary scan circuit generator. GenJTAG supports all the public instructions for the boundary scan technique, and also private instructions for other DFT techniques to be applied. Users can easily edit the generated boundary scan circuit code because it is described in behavioral level with the Verilog-HDL. GenJTAG has another advantage that any one can generate the boundary scan circuit by simply accessing to the web site.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.164-171
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• 1996

We report the experimental resutls on AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with carbon-doped base structure. To characterize the output power, load-pull mehtod was employed. By characterizing the devices with HP8510C, we extracted the small-signal equivalent circuit. The HBTs were fabricated employing wet mesa etching and lift-off process of ohmic metals. the implementation of polyimide into the fabriction process was accomplished to obtain the lower dielectric constant resultig in significant reduction of interconnect routing capacitance. The fabricated HBTs with an emitter area of 6${\times}14{\mu}m^{2}$ exhibited current gain of 45, BV$_{CEO}$ of 10V, cut-off frequency of 30GHz and power gain of 1 3dBm. To extract the small signal equivalent circuit, the de-embedded method was applied for parasitic parameters and the calculation of circuit equations for intrinsic parameters.