• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Korean Journal of Optics and Photonics
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• v.24 no.1
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• pp.1-8
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• 2013

In this paper, we report design, fabrication and characterization of the WBRM (Wide Band Receiver Module) for LADAR (LAser Detection And Ranging) application. The WBRM has been designed and fabricated using self-made APD (Avalanche Photodiode) and TIA (Trans-impedance Amplifier). The APD and TIA chips have been integrated on 12-pin TO8 header using self-made ceramic submount and circuit. The WBRM module showed 450 ps of rise time, and corresponding 780 MHz bandwidth. Furthermore, it showed very low output noise less than 0.8 mV, and higher SNR than 15 for 150 nW of MDS(Minimum Detectable Signal). To the author's knowledge, this is the best performance of an optical receiver module for LIDAR fabricated by 200 um InGaAs APD.

• Journal of Digital Convergence
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• v.14 no.5
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• pp.325-331
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• 2016

In driving at evening or night, we are not able to recognize the speed bump and so stop suddenly. It could result in accidents. And also, we have a restriction of street light installation in farm road because it could be harmful to the crops and driver could not recognize the walking people. It needs to develop the speed bump with light and streetlight to be non harmful to the crops. So, we develop both the speed bump and streetlight with LED which could be non harmful to the crops and be increased recognition of walking people in farm road. For LED lighting power, we use the solar cells, and piezoelectric elements. It has automatic on/off according to power saving rates without illumination sensor. Minimization of circuit elements and design of minimum resisters and low power LED was used for power saving in assuring 3-days.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2359-2368
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• 2013

In this paper, an IRD (internal read data) circuit preventing the reentry into the read mode while keeping the read-out DOUT datum at power-up even if noise such as glitches occurs at signal ports such as an input signal port RD (read) when a power IC is on, is proposed. Also, a pulsed WL (word line) driving method is used to prevent a DC current of several tens of micro amperes from flowing into the read transistor of a differential paired eFuse OTP cell. Thus, reliability is secured by preventing non-blown eFuse links from being blown by the EM (electro-migration). Furthermore, a compared output between a programmed datum and a read-out datum is outputted to the PFb (pass fail bar) pin while performing a sensing margin test with a variable pull-up load in consideration of resistance variation of a programmed eFuse in the program-verify-read mode. The layout size of the 8-bit eFuse OTP IP with a $0.18{\mu}m$ process is $189.625{\mu}m{\times}138.850{\mu}m(=0.0263mm^2)$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2369-2379
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• 2013

A CMOS x-ray line scan sensor which is used in both medical imaging and non-destructive diagnosis is designed. It has a pixel array of 512 columns ${\times}$ 4 rows and a built-in DC-DC converter. The pixel circuit is newly proposed to have three binning modes such as no binning, $2{\times}2$ binning, and $4{\times}4$ binning in order to select one of pixel sizes of $100{\mu}m$, $200{\mu}m$, and $400{\mu}m$. It is designed to output a fully differential image signal which is insensitive to power supply and input common mode noises. The layout size of the designed line scan sensor with a $0.18{\mu}m$ x-ray CMOS image sensor process is $51,304{\mu}m{\times}5,945{\mu}m$.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• Asian-Australasian Journal of Animal Sciences
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• v.16 no.10
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• pp.1443-1450
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• 2003

Crossbred (Bos taurus${\times}$Bos indicus) calves were used from birth till 14 weeks of age to evaluate three sources of protein that differed in ruminal degradability viz. groundnut cake alone (HD) or in combination with cottonseed meal (MD) and meat and bone meal (LD), when fed along with two sources of non-structural carbohydrates viz. raw (R) and thermally processed (P) maize. Twenty four new born calves were arranged in six groups in a $3{\times}2$ factorial design and fed on whole milk up to 56 d of age. All the different calves received calf startes along with green oats (Avena sativa) from 14 d of age onwards free-choice. A metabolism trial of 6d starters duration, conducted after 90 d of experimental feeding, revealed greater (p<0.05) digestibility of DM, OM, total carbohydrates, NDF and ADF in calves fed on the P diets than on the R diets promoting greater (p<0.05) metabolizable energy intake. The digestibility of NDF was higher (p<0.01) on LD diets where as calves on MD diets exhibited significantly lower digestibility of ADF (p<0.01). The retention of nitrogen per unit metabolic body size was significantly (p<0.05) higher on the LD-P diet than on the diet HD-P which, in turn, was higher (p<0.05) than that of HD-R. Nitrogen retention as percentage of intake was significantly greater (p<0.05) on LD-P than on LD-R diets (52.2 vs. 36.4%). Also, P fed calves utilized nitrogen more efficiently than the R fed as shown by retention of significantly greater proportions of intake (47.4 vs. 40.9%) and absorbed (65.8 vs. 59.5%) nitrogen. Calorimetric evaluation of the diets through open-circuit respiration chamber revealed that the dietary treatments had no impact on methane production by calves. The intake of DE and ME was improved (p<0.01) because of maize processing resulting in greater (p<0.01) retention of energy. The protein degradability exerted no influence on the partitioning or retention of energy. A significant interaction between cereal and protein types was evident with respect to retention of both nitrogen (p<0.01) and energy (p<0.05). In conclusion, no discernible trend in the influence of cereal processing was apparent on the dietary protein degradability, but the positive effect of cereal processing on energy retention diminished with the increase in dietary undegradability.

• Asian-Australasian Journal of Animal Sciences
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• v.31 no.6
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• pp.851-858
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• 2018

Objective: This study was conducted to compare different methods on effective energy evaluation of corn silage for beef cattle. Methods: Twenty Wandong bulls (Chinese indigenous yellow cattle) with initial body weight of $281{\pm}15.6kg$, were assigned to 1 of 5 dietary treatments with 4 animals per treatment in a randomized complete block design. Five dietary treatments included group 1 with corn silage only diet, group 2 with corn silage-concentrate basal diet (BD) and 3 groups with 3 test diets, which were the BD partly substituted by corn silage at 10%, 30%, and 60%. The total collection digestion trial was conducted for 5 d for each block after a 10-d adaptation period, and then an open-circuit respiratory cage was used to measure the gas exchange of each animal in a consecutive 4-d period. Results: The direct method-derived metabolizable energy and net energy of corn silage were 8.86 and 5.15 MJ/kg dry matter (DM), expressed as net energy requirement for maintenance and gain were 5.28 and 2.90 MJ/kg DM, respectively; the corresponding regression method-derived estimates were 8.96, 5.34, 5.37, and 2.98 MJ/kg DM, respectively. The direct method-derived estimates were not different (p>0.05) from those obtained using the regression method. Using substitution method, the nutrient apparent digestibility and effective energy values of corn silage varied with the increased corn silage substitution ratio (p<0.05). In addition, the corn silage estimates at the substitution ratio of 30% were similar to those estimated by direct and regression methods. Conclusion: In determining the energy value of corn silage using substitution method, there was a discrepancy between different substitution ratios, and the substitution ratio of 30% was more appropriate than 10% or 60% in the current study. The regression method based on multiple point substitution was more appropriate than single point substitution on energy evaluation of feedstuffs for beef cattle.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.11
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• pp.51-62
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• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.