• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.337-338
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• 2014

본 논문에서는 배터리 셀 간의 빠른 전하 균일화를 위한 새로운 셀 밸런싱 회로를 제안한다. 대칭적인 다권선 변압기를 이용하는 밸런싱 회로의 경우 셀들 간의 밸런싱 전류의 크기가 회로 내부 저항 및 변압기의 누설 인덕턴스에 의해 크게 제약 받고, 배터리 셀 간의 밸런싱이 이루어짐에 따라 충방전 전류가 감소한다는 단점이 있다. 본 논문에서는 보조 회로를 이용하여 밸런싱 전류를 부스트 업 시켜 빠르게 셀 간의 전하 밸런싱을 맞추어주는 회로를 제안한다. 이를 통해 회로 내부 저항의 영향을 줄이고 일정한 충방전 전류를 흘려보냄으로 빠르게 셀 전하들의 밸런싱을 맞출 수 있다.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.195-197
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• 1998

The large scale industry needs high voltage converters. Therefore series connection of power semiconductor devices is necessary. It is important to prevent a device induced the overvoltage above ratings by proper voltage balancing in the field of IGBT series connection. In addition, the overvoltage induced by a stray inductance has to be limited in the high power circuit. This paper proposes a new gate control scheme which can balance the voltage properly and limit the overshoot by control the slope of collector voltage under series connected IGBT turn-off transient. The propose gate control scheme limits the overvoltage by sensing the collector voltage and controlling the gate signal actively. The new series connected IGBT gate driver is made and its validity is verified by the experimental results for series connected IGBT circuit.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.96-105
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• 2021

Large-scale power converters consist of series or parallel module combinations. In these modular converter systems, the interleaving technique can be applied to improve capacitor reliability by reducing the ripple of the I/O current in which each module operates as a phase difference. However, when applying the interleaving technique for conventional three-level boost converters, the short-circuit period of the converter can be an obstacle. Such problem is caused by the absence of a low-level inductor of the conventional three-level boost converter. To solve this problem, a three-level boost converter with a low-level inductor is proposed and analyzed to enable interleaved operation. In the proposed circuit, the current ripple of the output capacitor depends on the neutral point connections between the modules. In this study, the ripple current is analyzed by the neutral point connections of the three-level boost converter that has a low-level inductor, and the effectiveness of the proposed circuit is proven by simulation and experiment.

• Journal of Biomedical Engineering Research
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• v.19 no.3
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• pp.251-260
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• 1998

The Holter monitoring system is a widely used noninvasive diagnostic tool for ambulatory patient who may be at risk from latent life-threatening cardiac abnormalities. In this paper, we design a high performance intelligent holter monitoring system which is characterized by the small-sized and the low-power consumption. The system hardware consists of one-chip microcontroller(68HC11E9), ECG preprocessing circuit, and flash memory card. ECG preprocessing circuit is made of ECG preamplifier with gain of 250, 500 and 1000, the bandpass filter with bandwidth of 0.05-100Hz, the auto-balancing circuit and the saturation-calibrating circuit to eliminate baseline wandering, ECG signal sampled at 240 samples/sec is converted to the digital signal. We use a linear recursive filter and preprocessing algorithm to detect the ECG parameters which are QRS complex, and Q-R-T points, ST-level, HR, QT interval. The long-term acquired ECG signals and diagnostic parameters are compressed by the MFan(Modified Fan) and the delta modulation method. To easily interface with the PC based analyzer program which is operated in DOS and Windows, the compressed data, that are compatible to FFS(flash file system) format, are stored at the flash memory card with SBF(symmetric block format).

• Journal of Electrical Engineering and Technology
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• v.6 no.3
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• pp.293-301
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• 2011

This paper presents a novel theoretical method based on power analysis to obtain voltage reference values for an inverter-based compensator. This type of compensator, which is installed in parallel with the load, is usually referred to as the active filter. The proposed method is tailored to design the compensator in such a way that it can simultaneously balance the asymmetric load, as well as correct the power factor of the supply side. For clarity, a static compensator is first considered and a recursive algorithm is utilized to calculate the reactance values. The algorithm is then extended to calculate voltage reference values when the compensator is inverter based. It is evident that the compensator would be asymmetric since the load is unbalanced. The salient feature associated with the proposed method is that the circuit representation of system load is not required and that the load is recognized just by its active and reactive consumptions. Hence, the type and connection of load do not matter. The validity and performance of the new approach are analyzed via a numerical example, and the obtained results are thoroughly discussed.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.2
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• pp.7-14
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• 2016

In this paper presents a low power algorithm using a feasible cluster generation method considered glitch. The proposed algorithm is a method for reducing power consumption of a given circuit. The algorithm consists of a feasible cluster generation process and glitches removal process. So that glitches are not generated for the node to which the switching operation occurs most frequently in order to reduce the power consumption is a method for generating a feasible cluster. A feasible cluster generation process consisted of a node value set, dividing the node, the node aligned with the feasible cluster generation. A feasible cluster generation procedure is produced from the highest number of nodes in the output. When exceeding the number of OR-terms of the inputs of the selected node CLB prevents the signal path is varied by the evenly divided. If there are nodes with the same number of outputs selected by the first highest number of nodes in the input produces a feasible cluster. Glitch removal process removes glitches through the path balancing in the same manner as [5]. Experimental results were compared with the proposed algorithm [5]. Number of blocks has been increased by 5%, the power consumption was reduced by 3%.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.391-396
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• 2022

In this study, a new voltage-balancing dual-active bridge converter that integrates a DAB converter with a voltage balancer is proposed for a bipolar DC distribution system. The proposed converter is configured to connect two loads to the transformer secondary center tap of the DAB converter, and no additional components are added. The proposed converter has the same operation as the conventional DAB converter, and it makes both output voltages similar. Moreover, the imbalanced current offset between the two loads is bypassed only on the secondary side of the transformer. Consequently, the proposed converter integrates a voltage balancer without any additional components, and no additional loss occurs in the corresponding components. Thus, high efficiency and high power density can be achieved. The feasibility of the proposed converter is verified using 3 kW prototypes under 380 V input and 190/190 V output conditions.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.10
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• pp.1275-1283
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• 1999

본 논문은 CMOS 디지털 회로에서의 전력 소모의 주원인인 신호의 천이중에서 회로의 동작에 직접적인 영향을 미치지 않는 불필요한 신호의 천이인 글리치를 줄이기 위한 효율적인 알고리즘을 제시한다. 제안된 알고리즘은 회로의 지연 증가 없이 게이트 사이징과 버퍼 삽입에 의해 경로 균등(path balancing)을 이룸으로써 글리치를 감소시킨다. 경로 균등화를 위하여 먼저 게이트 사이징을 통해 글리치의 감소와 동시에, 게이트 크기의 최적화를 통해 회로 전체의 캐패시턴스까지 줄일 수 있으며, 게이트 사이징 만으로 경로 균등화가 이루어지지 않을 경우 버퍼 삽입으로 경로 균등화를 이루게 된다. 버퍼 자체에 의한 전력 소모 증가보다 글리치 감소에 의한 전력 감소가 큰 버퍼를 선택하여 삽입한다. 이때 버퍼 삽입에 의한 전력 감소는 다른 버퍼의 삽입 상태에 따라 크게 달라질 수 있어 ILP (Integer Linear Program)를 이용하여 적은 버퍼 삽입으로 전력 감소를 최대화 할 수 있는 저전력 설계 시스템을 구현하였다. 제안된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 회로의 지연 증가 없이 평균적으로 30.4%의 전력 감소를 얻을 수 있었다.Abstract This paper presents an efficient algorithm for reducing glitches caused by spurious transitions in CMOS logic circuits. The proposed algorithm reduces glitches by achieving path balancing through gate sizing and buffer insertion. The gate sizing technique reduces not only glitches but also effective capacitance in the circuit. In the proposed algorithm, the buffers are inserted between the gates where power reduction achieved by glitch reduction is larger than the additional power consumed by the inserted buffers. To determine the location of buffer insertion, ILP (Integer Linear Program) has been employed in the proposed system. The proposed algorithm has been tested on LGSynth91 benchmark circuits. Experimental results show an average of 30.4% power reduction.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.5
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• pp.454-462
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• 2006

To enhance the competitive edge of the material cost, various techniques lowering the material cost of inverter to drive Cold Cathode Fluorescent Lamp (CCFL) have been developed. In this paper, the theoretical analysis has been done for the existing techniques such as Jin Balance and O2Micro technique. Especially, How to design the value of magnetizing inductance to meet the specification of the lamp current tolerance between lamps has been disclosed. Based on this result, two kinds of hybrid type balancing techniques have been proposed and analyzed mathematically, Also, the accuracy of the proposed techniques has been verified through Pspice simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.99-104
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• 1999

The large scale industry needs high voltage converters. Therefore series connection of power semiconductor devices is necessary. It is important to prevent the overvoltage from being induced across a device above ratings by the proper voltage balancing in the field of IGBT series connection. In addition, the overvoltage induced by a stray inductance has to be limited in the high power circuit. This paper proposes a new gate control scheme which can balance the voltage properly and limit the overshoot by controlling the slope of collector voltage under the turn-off transient in the series connected IGBTs. The proposed gate control scheme which senses the collector voltage and controls the gate signal actively limits the overvoltage. The new series connected IGBT gate driver is made and its validity is verified by the experimental results in the series connected IGBT circuit.