• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.36-39
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• 2000

The adaptive learning circuit is designed the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results is analyzed. The output frequency of the adaptive learning circuit is inversely proportioned to the source-drain resistance of MFSFET and the capacitance of the circuit. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of imput pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristics of the adaptive learning circuit, that is, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.162-167
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• 2012

This paper describes the design of a high-performance unified SVM classifier circuit. The proposed circuit supports both linear and non-linear SVM classifications. In order to ensure efficient classification, a 48x96 or 64x64 sliding window with 20 window strides is used. We reduced the circuit size by sharing most of the resources required for both types of classification. We described the proposed unified SVM classifier circuit using the Verilog HDL and synthesized the gate-level circuit using 65nm standard cell library. The synthesized circuit consists of 661,261 gates, operates at the maximum operating frequency of 152 MHz and processes up to 33.8 640x480 image frames per second.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.8
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• pp.299-309
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• 1984

This paper proposes the adapter for interrupting capacity augmentation of circuit breaker which can be applied in case of shortage in a existing circuit breaker's interrupting capacity due to utility system extension. The adapter utilizes two winding type of reactor instead of single winding type of reactor and the control of 2ry circuit is excuted by a triac interlocked with the system protective relays actuation so as to cut out the reactor by short circuit of the 2ry winding in normal situation and to cut in the reactor by open circuit of the 2ry winding in abnomal situation such as short circuit accident. As a result of the theoritical analysis and experiment, it is proved that the adaptor can reduce the voltage crop and iron loss due to the reactor signigicantly in normal system condition and do a role of reactor upon the power system accident.

• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.301-304
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• 2011

This paper describes the possibility of a low-power, high-resolution fingerprint sensor chip. A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than conventional circuit. The detection circuit is designed and simulated in 3.3V, 0.35${\mu}$m standard CMOS process, 40MHz condition. The result shows about 27% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is more stable and effective than a typical circuit.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.207-211
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• 2004

The performance of an inductive position sensor has approved by previous research papers. In this paper, magnetic circuit model of a ring-type multi-pole insuctive position sensor is described. The magnetic circuit model is required to design in ductive position sensor as well as draw a fault tolerance algorithm. Using the magnetic circuit theory, we derived the relationship between voltage applied and flux density in the normal air-gap. By idealizing the modulation/demodulation processes of signal processing circuit, sensor gain with respect to change of displacement is theoretically calculation using the magnetic circuit model, which validate the theoretical derivation.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.43-44
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• 2017

This paper presents design of auxiliary circuit to reduce loss of ZVT interleaved flyback converter. The ZVT interleaved converter using the conventional auxiliary circuit has a large conduction loss due to the constant circulating current in the auxiliary circuit. The auxiliary circuit proposed in this paper, which consists of the coupled inductor and DC-link capacitor, has linearly increasing or decreasing auxiliary current. Then, the conduction loss occurring in the auxiliary circuit is reduced. The validity of the proposed auxiliary circuit is verified with the prototype of 500W.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.8
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• pp.1-7
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• 2012

In this paper, a new LED driving circuit which is able to control dimming of LED is proposed using charge pump. The proposed LED driving circuit steps down the input voltage to operate LED without DC-DC converter. The operation of this driving circuit is verified by P-Spice simulation, and the characteristics of the driving circuit is measured and evaluated in the experiments. As a result, the driving circuit efficiency of 88.5[%] is obtained when all LEDs are turned on by digital control method at the highest dimming level(255/255).

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.66-71
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• 2009

A novel sensing scheme using resistive characteristics of the finger is proposed. ESD problem is more harmful than a capacitive fingerprint sensor in a resistive fingerprint sensor, because the sensor plate is directly connected to the sensing cell. The proposed circuit is more robust than conventional circuit for ESD. The sensor plate and sensing cell are isolated by capacitor. The pixel level simple detection circuit is fully digital operation unlike that of the capacitive sensing cell. The sensor circuit blocks are designed and simulated in a standard CMOS $0.35{\mu}m$ process. The proposed circuit is more stable and effective than a typical circuit.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• Proceedings of the KIPE Conference
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• 2004.07b
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• pp.704-708
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• 2004

Recently, many nation have released standard such as IEC 61000-3-2 and IEEE 59, which impose a limit on the harmonic current drawn by equipment connected to AC line in order to prevent the distortion of an AC Line. Therefore, Plasma Display Panel (PDP) which is highlightened in digital display device also has the Power Factor Correction (PFC) circuit to meet the harmonic requirements. In PDP power module, the conventional boost converter is usually used for the PFC circuit. However, it comes serious thermal problem on it's bridge diode due to heat of PDP, and therefore the system stability is not guaranteed. In this paper, the bridgeless boost converter, which is used for PFC circuit of the PDP power module, is designed and verified the possibility of the application in a practical product in a view of efficiency, component count, temperature and etc.