Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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Design of Low Power Capacitive Sensing Circuit with a High Resolution in CMOS Technology

  • Jung, Seung-Min (Department of Information Science and Telecommunications Eng., Hanshin University)
  • Received : 2011.05.02
  • Accepted : 2011.06.07
  • Published : 2011.06.30
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Abstract

This paper describes the possibility of a low-power, high-resolution fingerprint sensor chip. A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than conventional circuit. The detection circuit is designed and simulated in 3.3V, 0.35${\mu}$m standard CMOS process, 40MHz condition. The result shows about 27% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is more stable and effective than a typical circuit.

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References

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