• 제목/요약/키워드: chip-load

검색결과 225건 처리시간 0.028초

전자장비 회로기판의 열응력해석 (Thermal Stress Analysis for the Printed Circuit Board of Electronic Packages)

  • 권영주;김진안
    • 한국CDE학회논문집
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    • 제9권4호
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    • pp.416-424
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    • 2004
  • In this paper, the heat transfer analysis and thermal stress analysis of the PCB(Printed Circuit Board) equipped in electronic Packages are carried out for various may types of chips on the PCB. And two structural PCB models are used in the analyses. The electronic chips on the PCB usually emit heat and this heat generates the thermal stress around the chip. The thermal load due to the heat generation of chips on the PCB may cause the malfunction of the electronic packages such as a monitor. a computer etc. Hence, the PCB should be designed to withstand these thermal loads. In this paper, the heat transfer analysis and thermal stress analysis are executed for the PCB model with pins and the analysis results are compared with the results for the PCB model without pins. The analysis results show that the PCB model without pins is not good for the thermal stress analysis of PCB, even though these two models have similar heat transfer characteristics. The analysis results also show that the highest thermal stress occurs in the pin especially attached to the highest temperature chip, and the PCB constrained to the electronic package on the long side is structurally more stable than other cases. The analyses of the PCB are executed using the finite element analysis code, NISA.

Profibus-DP 프로토콜을 이용한 필드버스 시스템 구현 (Implementation of a Fieldbus System Based on Profibus-DP Protocol)

  • 배규성;김종배;최병욱;임계영
    • 제어로봇시스템학회논문지
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    • 제6권10호
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    • pp.903-910
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    • 2000
  • In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

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무전해 및 전해 도금법으로 제작된 ACF 접합용 니켈 범프 특성에 관한 연구 (A Study on the Characterization of Electroless and Electro Plated Nickel Bumps Fabricated for ACF Application)

  • 진경선;이원종
    • 마이크로전자및패키징학회지
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    • 제14권3호
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    • pp.21-27
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    • 2007
  • 이방성 전도필름(ACF) 접합에 사용되는 니켈 범프를 무전해 및 전해 도금법으로 제작한 다음, 이 범프들의 기계적 특성과 충격안전성을 압축시험, 범프전단시험, 낙하충격시험을 통하여 연구하였다. Nano indenter를 이용한 압축시험에서 얻은 하중-변형량 데이터를 변환시켜 니켈범프의 응력-변형량 곡선을 구하였다. 전해 니켈 범프는 무전해 니켈 범프에 비해 매우 작은 탄성한계응력과 탄성계수를 나타냈었다. 무전해 니켈 범프의 탄성한계응력과 탄성계수가 각각 600-800MPa, $9.7{\times}10^{-3}MPa/nm$인 반면 전해 니켈 범프의 경우에는 각각 70MPa, $7.8{\times}10^4MPa/nm$이었다. 범프전단 시험에서 무전해 니켈 범프는 소성변형이 거의 일어나지 않고 낮은 전단하중에서 범프가 패드 층에서 튕기듯이 떨어져 나간 반면 전해 니켈 범프는 큰 소성변형을 일으키며 범프가 잘려나갔으며 높은 전단하중을 보여주었다. 낙하충격시험 결과 ACF 플립칩 방법으로 본딩한 무전해 및 전해 범프 모두 높은 충격 신뢰성을 보였다.

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온칩 다이오드를 이용한 빛에너지 하베스팅 회로 설계 (Design of a Photo Energy Harvesting Circuit Using On-chip Diodes)

  • 윤은정;황인호;박준호;박종태;유종근
    • 한국정보통신학회논문지
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    • 제16권3호
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    • pp.549-557
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    • 2012
  • 본 논문에서는 CMOS 공정의 p-diff/n-well 다이오드만을 사용한 ISC(Integrated Solar Cell)를 이용하여 MPPT(Maximum Power Point Tracking) 제어 기능을 갖는 온칩 빛에너지 하베스팅 시스템을 제안하였다. MPPT 제어는 PV(Photovoltaic) 셀의 개방전압과 MPP(Maximum Power Point) 전압간의 비례관계를 이용하여, 작은 pilot PV 셀로 하여금 main PV 셀의 MPP를 실시간 추적할 수 있도록 설계하였다. 모의실험 결과 설계된 회로는 MPPT 제어기능을 적용했을 때 부하가 큰 경우에도 MPP 근처의 전압을 부하에 공급함으로써 부하에 연결된 회로가 정상적으로 동작하는 것을 확인하였다. 제안된 회로는 0.18um CMOS 공정으로 설계하였으며, main PV 셀과 pilot PV 셀의 면적은 각각 $8mm^2$$0.4mm^2$이다.

An Operating Frequency Independent Energy Measurement Technique for High Speed Microprocessors

  • Thongnoo, Krerkchai;Changtong, Kusumal
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2004년도 ICCAS
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    • pp.2051-2054
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    • 2004
  • This paper proposes a more accurate task level energy measurement technique for high speed microprocessors. The technique is based on the relationship of the amount of current consumed by the microprocessor and the pulse width of the power supply controller chip, employed in the synchronous buck DC-DC converter in the microprocessor's power supply. The accuracy of the measurement is accomplished by measuring variation in pulse width in each power supply cycle. The major advantage of this technique is that its accuracy does not depend on the operating frequency of the microprocessor. To prove the proposed technique, we implemented the measurement unit of the microprocessor energy meter using an FPGA chip operating at 50 MHz. Both static and dynamic load measurement are tested in order to obtain some behaviours. Moreover, various commercially available mainboards which employ synchronous buck regulators at 200 KHz switching frequency, were measured. The results agree with previous works with better accuracy at higher operating frequency.

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FPGA를 이용한 심전도 전처리용 적응필터 설계 (Design of FPGA Adaptive Filter for ECG Signal Preprocessing)

  • 한상돈;전대근;이경중;윤형로
    • 대한의용생체공학회:의공학회지
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    • 제22권3호
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    • pp.285-291
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    • 2001
  • In this paper, we designed two preprocessing adaptive filter - high pass filter and notch filter - using FPGA. For minimizing the calculation load of multi-channel and high-resolution ECG system, we utilize FPGA rather than digital signal processing chip. To implement the designed filters in FPGA, we utilize FPGA design tool(Altera corporation, MAX-PLUS II) and CSE database as test data. In order to evaluate the performance in terms of processing time, we compared the designed filters with the digital filters implemented by ADSP21061(Analog Devices). As a result, the filters implemented by FPGA showed better performance than the filters based on ADSP21061. As a consequence of examination, we conclude that FPGA is a useful solution in multi-channel and high-resolution signal processing.

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DIGITAL FILTER ONE CHIP I.C.화 및 제작 (Design of Digital Filter One Chip I.C)

  • 박상봉;백인천;박노경;문대철;차균현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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    • pp.1495-1498
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    • 1987
  • This paper described the design of register part, ROM and entire digital filter implementation by merging with ALU, control part last year. The register part consists of shift register, parallel load serial output register, multiplexer and selector, and we designed specially the 1024 memory cells ROM and decoder to decode the register data. Also, presented scaling algorithm to prevent the overflow.

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Distributed ECU System Design for High Speed and High Precision Control of a Marine Engine

  • Lee, Jong-Nyun
    • Journal of information and communication convergence engineering
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    • 제8권5호
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    • pp.534-538
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    • 2010
  • Efficient control of a marine engine requires an engine control unit (ECU) system that handles fast and precise signal processes for in-coming and out-going signals from fast running engines. In order to handle these roles, the sequential control has been adapted in the ECU system in small and medium size ship engines, which has caused high production cost and complexity of the system. Hence, this paper is focused on developing an distributed ECU system for high speed and high precision control of a marine engine by efficiently combining a CPLD chip and a microprocessor. By sharing load at the MCU with the designed CPLD chip, we could achieve in driving a marine engine with high speed and precise control so that the ECU board has been simplified and its production cost has been reduced.

A Study of On-Chip Voltage Down Converter for Semiconductor Devices

  • Seo, Hae-Jun;Kim, Young-Woon;Cho, Tae-Won
    • 전기전자학회논문지
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    • 제12권1호
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    • pp.34-42
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    • 2008
  • This paper proposes a new on-chip voltage down converter(VDC), which employs a new reference voltage generator(RVG). The converter adopts a temperature-independence reference voltage generator, and a voltage-up converter. The architecture of the proposed VDC has a high-precision, and it was verified based on a 0.25${\mu}m$ 1P5M standard CMOS technology. For 2.5V to 1.0V conversion, the RVG circuit has a good characteristics such as temperature dependency of only 0.2mV/$^{\circ}C$, and the voltage-up circuit has a good voltage deviation within ${\pm}$0.12% for ${\pm}$5% variation of supply voltage VDD. The output voltage is stabilized with ${\pm}$1mV for load current varying from 0 to 100mA.

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환경 친화적인 세미드라이 선삭가공 특성 (Characteristics of Environment-friendly Semi-dry Turning)

  • 이종항;오종석
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1997년도 추계학술대회 논문집
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    • pp.385-388
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    • 1997
  • As the environmental regulations become stricter, new machining technologies are being developed which takes envi ronmenta 1 aspects into account . Since cut t ing oi I has some impact on environment. many researches are being carried out to minimize the use of cutting oi I. The methods for minimizing cutting oil usage includes the following techniques: I ) Cooling of tools and work piece. 2) Useage of compressed cooling air for the removal of chip. 3) Minimal useage of environment-friendly vegetable cutt:ngoiI for lubrication between chip and tools. Since the turning machine is continuous, tools are under constant thermal load and tool wear increases as the lubricative performance degrades. Also surface roughnesses have a direct influence on turning. In order to examine the characteristics of turningmachining, this work investigates experimentally the degree of tool wear and characteristics of surface roughness in relation to machining conditions, supply methods, and cooling methods.

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