• 한국산업융합학회 논문집
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• 제2권2호
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• pp.131-137
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• 1999

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the energy release rate criterion. The package crack formation depend on various parameters such as chip set, chip size, package thickness, package width, material properties and the moisture content etc. The effects of chip set and the other parameters were estimated during the analysis of package cracks which were located in the edge of the upper interface of the chip and the lower interlace of the die pad. From the results, it could be obtained that the more significant parameters to effect the chip set are chip width.

• 한국진공학회지
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• 제21권4호
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• pp.185-192
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• 2012

Light Emitting Diode (LED) 칩의 크기는 전도를 통한 열의 방출에 있어 면적의 확대로 인한 열 밀도의 감소와 칩의 외부양자효율 변화로 인하여 LED 칩의 p-n 정션 온도와 패키지의 열 저항에 영향을 미친다. 본 연구에서는 16칩 LED 패키지에서 칩의 크기가 0.6 mm와 1 mm인 두 가지 경우에 대하여 순전압(forward voltage)을 측정하였고, 순간열분석법(thermal transient analysis)을 이용하여 정션 온도와 열 저항을 평가하였으며, 이를 LED 칩의 전기적인 특성과 LED 패키지의 구조적인 특성과 연관하여 해석하였다.

• 전기학회논문지
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• 제58권1호
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• 한국전자파학회논문지
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• 제16권1호
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• pp.102-112
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• 2005

본 논문에서는 CSP(Chip Size Package)를 이용하여 정합소자 및 모든 바이어스소자, ESD(Electrostatic Dis-charge) 보호소자를 MMIC상에 완전집적한 K/Ka밴드 광대역 MMIC chip set에 관하여 보고한다. CSP에 대해서는 이방성 도전필름인 ACF(Anisotropic Conductive Film)를 이용하였으며, 그 결과 MMIC 패키지 프로세스가 간략화 되었고, CSP MMIC의 저 가격화가 실현되었다. MMIC상에 집적하기 위한 DC 바이어스 용량소자로서는 고유전율의 $STO(SrTi_{3})$ 필름 커패시터가 이용되었으며, DC 피드소자와 ESD 보호소자로서는 LC 병렬회로가 사용되었다. 그리고, K/KA 밴드 광대역에 걸친 MMIC의 정합과 안정도를 위해서는 프리매칭회로와 RC 병렬회로가 이용되었으며, 제작된 CSP MMIC는 광대역(K/Ka) 밴드에서 양호한 RF 특성을 보였다. 본 논문은 K/Ka 밴드의 주파수 대역에 있어서의 완전집적화 CSP MMIC 칩셋에 관한 최초의 보고이다.

• 한국공작기계학회논문집
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• 제11권3호
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• pp.28-32
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• 2002

Recently, the miniature of electric products such as notebook, cellular-phone etc. is apparently appeared, due to the smaller size of the semiconductor chips. As the size of chip gets smaller, the circuit could be easily damaged by the slightest influence, therefore it is important to investigate the machining quality of $\mu$ BGA. This paper deals with machining characteristics of the $\mu$ BGA singulation. The relationships between the singulation face and machining quality of the $\mu$ BGA singulation are investigated. It is confirmed that machining quality improves as the singulation force decreases.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 1999년도 1st Korea-Japan Advanced Semiconductor Packaging Technology Seminar
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• pp.127-154
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• 1999

Interconnect - Wire bonding-> Flip chip interconnect ; At research step, Au stud bump bonding seems to be more proper .Package -Plastic package-> $Z_{0}$ controlled land grid package -Flip Chip will be used for RF ICs and CSP for digital ICs -RF MCM comprised of bare active devices and integrated passive components -Electrical design skills are much more required in RF packaging .Passive Component -discrete-> integrated -Both of size and numbers of passive components must be reduced

• 한국항해항만학회지
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• 제27권2호
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• pp.217-221
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• 2003

본 논문에서는 새로운 형태의 CSP (chip site package)를 이용하여 정합소자 린 바이어스소자를 MMIC상에 완전집적한 Ku/K밴드 광대역 증폭기 MMIC에 관하여 보고한다. 새로운 형태의 CSP에 대해서는 이방성 도전필름인 ACF (anisotropic conductive film)을 이용하였으며, 그 결과 MMIC 패키지 프로세스가 간략화 되었고, CSP MMIC의 저 가격화가 실현되었다. MMIC상에 집적하기 위한 DC 바이어스 용량소자로서는 고유전율의 STO (SrTiO3) 필름 커패시터가 이용되었다. 제작된 CSP MMIC는 광대역 RF동작특성 (12-24 GHz에서 12.5$\pm$1.5 dB의 이득치, -6 dB이하의 반사계수, 18.5$\pm$1.5 dBm의 PldB) 을 보였다. 본 논문은 K 또는 Ku 밴드의 주파수대역에 있어서의 완전집적화 CSP MMIC에 관한 최초의 보고이다.

• 대한기계학회논문집A
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• 제21권6호
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• pp.951-960
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• 1997

Package crack caused by the soldering process in the surface mounting plastic package is evaluated by applying the maximum energy release rate criterion. It could be shown that the crack propagation from the lower edge of the ie pad is easily occurred at the maximum temperature during the soldering process, where the pressure acting on the crack surface is assumed by the saturated vapor pressure at maximum temperature. The package crack formation depends on various parameters such as chip size, relative thickness, material properties, the moisture content and soldering temperature etc. The quantitative measure of the effects of the parameters could be easily obtained by using the taguchi's method which requires only a few kinds of combinations with such parameters. From the results, it could be obtained that the more significant parameters to effect the package reliability are the orders of Young's modulus, die pad size, down set, chip thickness and maximum soldering temperature.

• International Journal of Quality Innovation
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• 제8권3호
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• pp.81-112
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• 2007

In the competitive global market, firms have to keep profit from innovation activities. A firm makes profits by offering products or services at a lower cost than its competitors or by offering differentiated products at premium prices that more than compensate for the extra cost of differentiation. The IC Package and Testing technology industries were the first high technological industry to build in Taiwan. The Package and Testing industries in Taiwan adopted competitive innovation activities to become stronger. In our study, we want to know how innovation activities influence a firm operating in the IC Package and Testing industries. Our study used a questionnaire and Likert five-point scale to survey the innovation activities, customer and feedback in innovation performance in the IC Package and Testing industry. The wafer level chip size packing technology in our study indicates the innovation activities. Because we need to compare the difference between the wafer level chip size packing technology and wire bonding technology to recognize innovation and how the innovator and customer were influenced. Our conclusions are described below: (1) When the innovator adopts innovation activities that can be maintained using experiments and knowledge, using machine and decision variables more quickly will produce success; (2) Innovators should adopt innovation activities that focus on customers that use knowledge and experimentation, training time and cost. If an innovation forces customers to spend much time and cost to learn new technology or applications, the innovation will not be adopted; (3) Innovators that create innovation performance higher than his customers must also consider the impact upon their customers. We have to remind innovator to focus on why their customers have a different level of evolution in the same innovation activities.

• Tribology and Lubricants
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• 제21권2호
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• pp.71-76
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• 2005

This paper compares of mechanical tensile properties of 6 kinds of copper foil. The beam lead made with copper foil. Different from other package type such as plastic package, Chip Size Package has a reliability problem in beam lead rather than solder joint in board level. A new tensile loading system was developed using voice-coil actuator. The new tensile loading system has a load cell with maximum capacity of 20 N and a non-contact position measuring system based on the principle of capacitance micrometry with 0.1nm resolution for displacement measurement. Strain was calculated from the measured displacement using FE analysis. The comparison of mechanical properties helps designer of package to choose copper for ensuring reliability of beam lead in early stage of semiconductor development.