• The Journal of the Korea Contents Association
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• v.6 no.9
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• pp.98-107
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• 2006

By improving performance of mobile machine(3D engine, 3D accelerator chip set, etc) and developing wireless network technology, a demand for actual contents of users is being increased rapidly. But, there are some difficulties yet for the speedy development of actual contents because of the limitation of development resources that is dependent on each mobile device's different performance. In general, much of the animated character-creation work for mobile environment is still done manually by experienced animator with the method of key frame processing. However, it needs a lot of time and more costs for creating motion. Additionally, it is possible to cause a distortion of motion. In this paper, I solved the difficulties by using a optical motion capture system, it was able to acquire accurate motion data more easily and quickly, and then it was possible to make 3D dance contents efficiently. Also, I showed techniques of key reduction and controlling frame number for using huge amounts of motion capture data in mobile environment which requires less resources. In making 3D dance contents, using an optical motion capture system was verified that it was more efficient to make and use actual-reality contents by creating actual character motion and by decreasing processing time than existing method.

• Journal of Korean Society of Forest Science
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• v.110 no.2
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• pp.217-232
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• 2021

This study calculated the productivity and cost of extraction and processing of logging residues by cut-to-length (CTL) and whole-tree (WT) harvesting methods. In addition, the comparative analysis of the characteristics of wood chip fuel to examine whether it was suitable for the fuel conditions of the energy facility. In the harvesting and processing system to produce the wood chips of logging residues the system productivity and cost of the CTL harvesting system were 1.6 Gwt/SMH and 89,865 won/Gwt, respectively. The productivity and cost of the WT harvesting system were 2.9 Gwt/SMH and 72,974 won/Gwt, respectively. The WT harvesting productivity increased 1.3times while harvesting cost decreased by 18.7% compared to the CTL harvesting system. The logging residues of wood chips were not suitable for CTL wood chips based on International Organization for Standardization (ISO 17225-4:2021) and South Korea standard (NIFoS, 2020), but the quality (A2, Second class) was improved through screening operation. The WT-unscreened wood chips conformed to NIFoS standard (second class) and did not conform to ISO but were improved through screening operation (Second class). In addition to the energy facility in plant A, all wood chips except CTL-unscreened wood chips were available through drying processing. The WT-unscreened wood chips were the lowest at 99,408 won/Gwt. Plants B, C, and D had higher moisture content than plant A, so WT-unscreened wood chips without drying processing were the lowest at 57,204 won/Gwt. Therefore, the production of logging residues should improve with operation methods that improve the quality of wood chips required for applying the variable biomass and energy facility.

• Journal of Korean Society of Forest Science
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• v.98 no.4
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• pp.426-434
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• 2009

This study was carried out to derive the most optimal production process for the wood fuels(chip and pellet), by collecting cost data on each procedure through the life cycle assessment approach, and to compare between the profitability and efficiency, from the view points of producers and consumers, irrespectively. The costs accounted in this analysis were based on the opportunity cost. The results show that wood chips are cheaper than wood pellets in production costs. In respect to the process with the lowest production cost, while wood chips should be to crush collected residues into pieces on the spot for merchandizing, wood pellets need to be transported to manufactory for pelletizing. The study findings also include that the profits, which is estimated by subtracting expenses from gained sale revenue, were a bit higher for wood chips than wood pellets. Additionally, the price ratio of wood pellets to wood chips for getting the same caloric value appears to be 1.27. Despite of economic benefits of processing wood chips, there are several problems in practice. For producers, there is a possible increase in not only transportation cost for conveying crushers to the dispersed places, but storage cost due to the lack of the marketplaces in the immediate surroundings. For consumers, on the other hand, there are some challenging issues, such as bulky storage facility requirement, additional labor for fuel supplement, frequent ashes disposal, and decomposition in summer and freezing in winter caused by wood chips' own moisture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.5
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• pp.51-57
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• 2015

In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.39-46
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• 2016

This paper describes the third order feedforward delta-sigma modulator with inverter-based integrators and a 1.5bit comparator for the application of audio signal processing. The proposed 3rd-order delta-sigma modulator is multi-bit structure using 1.5 bit comparator instead of operational amplifier. This delta-sigma modulator has high SNR compared with single-bit 4th-order delta-sigma modulator in a low OSR. And it minimizes power consumes and simplified circuit structure using inverter-based integrator and using inverter-based integrator as analogue adder. The modulator was designed with 0.18um CMOS standard process and total chip area is $0.36mm^2$. The measured power cosumption is 28.8uW in a 0.8V analog supply and 66.6uW in a 1.8V digital supply. The measurement result shows that the peak SNDR of 80.7 dB, the ENOB of 13.1bit and the dynamic range of 86.1 dB with an input signal frequency of 2.5kHz, a sampling frequency of 2.56MHz and an oversampling rate of 64. The FOM (Walden) from the measurement result is 269 fJ/step, FOM (Schreier) was calculated as 169.3 dB.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.1
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• pp.26-34
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• 1999

According to increase of nonlinear power electronics equipment, active power filters have been researched and developed for many years to compensate harmonic disturbances and reactive power. However the commercial of active power filter is being proceeded slowly, because the cost of active power filter compared to the passive filter for harmonic and reactive power compensation is expensive. Especially, the use of DSP (Digital Signal Processing) chip, which is frequently used to control 3-phase active power filter, is a factor of increasing the cost of active power filters. On the other hand, the use of only analog controller makes the controller's circuits much more complicate and depreciates the flexibilities of controller. In this paper, a controller with low cost for 5[kVA] 3-phase active power filter system is designed. To reduce the expense of active filter system, the presented controller is composed of digital control part using Intel 80C196KC $\mu$P and analog control part using hysteresis controller for current control. Characteristic analysis of designed controller for active filter system is performed by computer simulation and compensating characteristics of the designed controller are verified by experiment.tegy can apply to the vector control, leading to better output torque capability in the ac motor drive system. This strategy is that in the overmodulation range, the d-axis output current is given a priority to regulate the flux well, instead the q-axis output curent is sacrificed. Therefore, the vector control even in the overmodulation PWM operation can be achieved well. For this purpose, the d-axis output voltage of a current controller to control the flux is conserved. the q-axis output voltage to control the torque is controlled to place the reference voltage vector on the hexagon boundary in case of the overmodulation. The validity of the proposed overall scheme is confirmed by simulation and experiments for a 22[kW] induction motor drive system.

• The KIPS Transactions:PartD
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• v.11D no.1
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• pp.11-22
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• 2004

As random access memory chip gets cheaper, it becomes affordable to realize main memory-based database systems. Consequently, reducing cache misses emerges as the most important issue in current main memory databases, in which CPU speeds have been increasing at 60% per year, compared to the memory speeds at 10% per you. In this paper, we design and implement a main-memory database system for real-time mobile GIS. Our system is composed of 5 modules： the interface manager provides the interface for PDA users； the memory data manager controls spatial and non-spatial data in main-memory using virtual memory techniques； the query manager processes spatial and non-spatial query : the index manager manages the MR-tree index for spatial data and the T-tree index for non-spatial index : the GIS server interface provides the interface with disk-based GIS. The MR-tree proposed propagates node splits upward only if one of the internal nodes on the insertion path has empty space. Thus, the internal nodes of the MR-tree are almost 100% full. Our experimental study shows that the two-dimensional MR-tree performs search up to 2.4 times faster than the ordinary R-tree. To use virtual memory techniques, the memory data manager uses page tables for spatial data, non- spatial data, T-tree and MR-tree. And, it uses indirect addressing techniques for fast reloading from disk.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.514-526
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• 2004

Microarray is a new technique for gene expression experiment, which has gained biologist's attention for recent years. This technology enables us to obtain hundreds and thousands of expression of gene or genotype at once using microarray Since it requires manual work to analyze patterns of gene expression, we want to develop an effective and automated tools to analyze microarray image. However it is difficult to analyze DNA chip images automatically due to several problems such as the variation of spot position, the irregularity of spot shape and size, and sample contamination. Especially, one of the most difficult problems in microarray analysis is the block and spot addressing, which is performed by manual or semi automated work in all the commercial tools. In this paper we propose a new algorithm to address the position of spot and block using a new concept of regular structure grid searching. In our algorithm, first we construct maximal I-regular sequences from the set of input points. Secondly we calculate the rotational angle and unit distance. Finally, we construct I-regularity graph by allowing pseudo points and then we compute the spot/block address using this graph. Experiment results showed that our algorithm is highly robust and reliable. Supplement information is available on http://jade.cs.pusan.ac.kr/~autogrid.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.18 no.1
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• pp.21-31
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• 2017

In this paper, the Zynq system-on-chip (SoC) platform is used to design an adaptive noise reduction and edge-detection system using partial reconfiguration. Filters are implemented in a partially reconfigurable (PR) region to provide high computational complexity in real-time, 1080p video processing. In addition, partial reconfiguration enables better utilization of hardware resources in the embedded system from autonomous replacement of filters in the same PR region. The proposed edge-detection system performs adaptive noise reduction if the noise density level in the incoming video sequences exceeds a given threshold value. Results of implementation show that the proposed system improves the accuracy of edge-detection results (14~20 times in Pratt's Figure of Merit) through self-reconfiguration of filter bitstreams triggered by noise density level in the video sequences. In addition, the ZyCAP controller implemented in this paper enables about 2.1 times faster reconfiguration when compared to a PCAP controller.