• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1254-1258
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• 2004

This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.707-710
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• 2005

In this paper, we propose a new communication network for on-chip communication. The network is based on a direct sequence code division multiple access (DS-CDMA) technique. The new communication network is suitable for a parallel processing system and also drastically reduces the I/O pin count. Our network architecture is mainly divided into a CDMA-based network interface (CNI), a communication channel, a synchronizer. The network includes a reverse communication channel for reducing latency. The network decouples computation task from communication task by the CNI. An extreme truncation is considered to simplify the communication link. For the scalability of the network, we use a PN-code reuse method and a hierarchical structure. The network elements have a modular architecture. The communication network is done using fully synthesizable Verilog HDL to enhance the portability between process technologies.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(1)
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• pp.123-126
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• 2004

Demands on dealing with multimedia data through the network have been increased, and networking multimedia devices require processing, transmitting , and receiving the digital data. In order to implement the network for high performance and low cost, we may have to integrate the dedicated hardware into a system on a chip by spending an extra amount of silicon resource. In this paper, we describe hardware implementation of TCP/IP protocol stack which is now popular to connect multiple PCs and peripherals by means of networks. For evaluation we used ALTERA APEX 20K600EBC652 FPGA with 600,000 gates. The operating frequency is estimated 29.9MHz and it used area of $26\%$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.127-138
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• 2012

In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• IEIE Transactions on Smart Processing and Computing
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• 제4권1호
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• pp.59-63
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• 2015

This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with a shared Multiplying DAC. Using shared MDAC, the total capacitance in the SAR ADC decreased by 93.75%. The proposed ADC consumed 2.28mW under a 1.2V supply and achieved 9.679 bit ENOB performance. The ADC was implemented in $0.13{\mu}m$ CMOS technology. The chip area was $760{\times}280{\mu}m^2$.

• 한국기계가공학회지
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• 제1권1호
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• pp.109-116
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• 2002

Resently, reduction of industrial products in size and weight has increased by the application of micro-drill for gadgets of high precision and gave rise to a great interest in a micro-drilling. Due to the lack of tool stiffness and the chip packing, micro-drilling requires not only the robust tool structure which has not affected by the vibration, but also the effective drilling methods designed to prevent tool fracture from cutting troubles. Firstly, this paper presents a new manufacturing process of micro-drill for improving the product rate and an optimum shape of micro-drill for lengthening the tool life, and secondly suggests between tool life and drilling torque acquired in the inprocess monitoring system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.439-440
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• 2008

모터의 정밀한 제어를 위해서 홀센서와 모터의 회전자 위치를 검출해내는 엔코더의 사용이 필수적이라 할 수 있다. 본 논문에서는 BLAC모터의 회전자 위치검출 방법으로 자석과 디지털 신호처리 칩을 이용하여 엔코더와 홀센선의 기능을 구현하였다. 이러한 방법의 장점은 기구적인 구조가 단순하여 저가로 구현할 수 있다는 것이다. 단순 2극 자석이 칩의 중심점을 축으로 회전하면 칩 중심 부위의 통합적 홀소자가 칩 표면 자기장을 전압으로 변환한다. 이 신호를 받아 DSP의 아날로그/디지털 변환 기능을 이용하여 절대각도 위치 정보를 검출해내어 기존의 엔코더 성능을 대치하는 연구과정을 본 논문에서 보였다.

• Journal of information and communication convergence engineering
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• 제15권3호
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• pp.151-159
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• 2017

Steganography, which is popular as an image processing technology, is the art of using digital images to hide a secret message in such a way that its existence can only be discovered by the sender and the intended receiver. This technique has the advantage of concealing secret information in a cover medium without drawing attention to it, unlike cryptography, which tries to convert data into something messy or meaningless. In this paper, we propose two efficient least significant bit (LSB)-based steganography techniques for designing an image-based steganography system on chip using hardware description language (HDL). The proposed techniques manipulate the LSB plane of the cover image to embed text inside it. The output of these algorithms is a stego-image which has the same quality as that of the original image. We also implement the proposed techniques using the Altera field programmable gate array (FPGA) and Quartus II design software.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2007년도 춘계학술대회A
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• pp.1517-1521
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• 2007

On this study, technical aspects were reviewed to drill a series of micro holes (${\phi}$0.10) over 200 within a few micron tolerance in diameter and position on the stainless steel material. Dedicated tools & jigs were designed and manufactured and optimum cutting conditions were found. On this micro hole drilling process, guide drill and step feeding were applied to help chip discharge, prevent drill breakage and finally improve the accuracy of positioning and roundness. The processing results indicated that most holes are distributed within a few micron tolerance in diameter and position intervals.