• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.321-325
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• 2009

The detection process of defective tags in most of Korean domestic RFID manufacturing companies is handled or treated by on-hand processing after the job of chip bonding, so it has been requesting to reduce the time and cost for manufacturing of RFID tags. Therefore, in this paper, we design and implement the system to perform the functionality of detection of defective tags after the process of chip bonding, and so provide the basis of a related software to establish the foundation of a automation system for the detection of defected RFID tags which is requested in the related Korean domestic industrial field. The developed system in this paper shows the enhancement of 700% in processing speed and 100% in detection rate of defective tags, comparing to the method of on-hand processing.

• Smart Media Journal
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• v.11 no.11
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• pp.25-31
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• 2022

Deep learning-based image processing is essential for autonomous vehicles. To process road images in real-time in a System-on-Chip (SoC) environment, we need to execute deep learning models on a NPU (Neural Procesing Units) specialized for deep learning operations. In this study, we imported seven open-source image processing deep learning models, that were developed on GPU servers, to Texas Instrument Deep Learning (TIDL) NPU environment. We confirmed that the models imported in this study operate normally in the SoC virtual environment through performance evaluation and visualization. This paper introduces the problems that occurred during the migration process due to the limitations of NPU environment and how to solve them, and thereby, presents a reference case worth referring to for developers and researchers who want to port deep learning models to SoC environments.

• Journal of the Optical Society of Korea
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• v.15 no.3
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• pp.264-271
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• 2011

In this paper we examine and compare the computational speeds of three-dimensional (3D) object recognition by use of digital holography based on central unit processing (CPU) and graphic processing unit (GPU) computing. The holographic fringe pattern of a 3D object is obtained using an in-line interferometry setup. The Fourier matched filters are applied to the complex image reconstructed from the holographic fringe pattern using a GPU chip for real-time 3D object recognition. It is shown that the computational speed of the 3D object recognition using GPU computing is significantly faster than that of the CPU computing. To the best of our knowledge, this is the first report on comparisons of the calculation time of the 3D object recognition based on the digital holography with CPU vs GPU computing.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1764-1767
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• 2003

It is widely used in composite materials like several mechanical parts. aerospace industries. internal and structural materials of cars, building structures. ship materials and sporting goods. but it is insufficient to apply in field of mechanical processing. Therefore. GFRP which is possible to use in industrial field was examined about cutting force. tool wear condition of cutting, chip shape. surface roughness and inlet or outlet shape of processing parts with changing cutting condition and using HSS drill which is in vertical machining center in this paper.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.963-971
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• 1990

This paper proposes a memory intensive VLSI architecture for the realization of real-time 3x3 neighborhood processor based on the distributed arithmetic. The proposed architecture is characterized by a bit serial and multi-kernel parallel processing which exploits the pixel kernel parallelism and concurrency. The chip implements 8 neighborhood processing elements in parallel with efficirnt input and output modules which operate concurrently. Besides the a4chitectural design of a neighborhood processor, the design methodology using module generator concept has been considered and MOGOT(MOdule Generator Oriented VLSI design Tool) has been constructed based on the workstation. Based on these design environments MOGOT, it has been shown that the main part of the suggested architecture can be designed efficiently using 2\ulcorner double metal CMOS technology. It includes design of input delay and data conversion module, look-up table for inner product operation, carry save accumulator, output data converter and delay module, and control module.

• The Journal of the Acoustical Society of Korea
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• v.15 no.3E
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• pp.13-18
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• 1996

A real-time identifier for the nonstationary time-varying signals and systems was implemented using a low cost DSP (digital signal processing) chip. The identifier is comprised of I/O units, a central processing unit, a control unit and its supporting software. In order t estimate the system accurately and to reduce quantization error during arithmetic operation, the firmware was programmed with 64-bit extended precision arithmetic. The performance of the identifier was verified by comparing with the simulation results. The implemented real-time identifier has negligible quantization errors and its real-time processing capability crresponds to 0.6kHz for the nonstationary AR (autoregressive) model with n=4 and m=1.

• Proceedings of the Korean Society of Laser Processing Conference
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• 2006.11a
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• pp.103-107
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• 2006

Decapsulation of EMC(Epoxy Molding Compound) in package device is a method used to inspect inside of device by removing plastic molding. So far, chemical etching and mechanical grinding methods have been used widely. Recently, several works using laser have been carried out. This method has advantages with fast process time and precision than conventional methods because of noncontact process. Also, laser process is a clean process because of removing EMC directly without using toxic chemicals. The wavelength of laser used in this study is 355nm. Key parameters of removing EMC are laser power, scan speed, and number of scans of laser. It if confirmed that laser decapsulation is a useful process to inspect inside a device with a small thermal damage to chip surface.

• ETRI Journal
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• v.30 no.4
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• pp.495-505
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• 2008

This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial, $1+x^2+x^5$, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.917-919
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• 2011

Recently, most network communication chips are powered; which causes power consumption a heavily constraint. Since, there are a lot of expectations on TPM to have a high performance in terms of authentication of its device. During the design process there is a need to estimate the security of the design but it always when the chip has already been manufactured. This paper designed a power consumption control monitor in TPM device which evaluate the voltage drop during processing of use. Therefore we will analyze the power consumption profile. The result shows that the voltage drop leads to vulnerability of the system to attackers during communication process.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.536-539
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• 2002

In this paper, we developed the automatic optical fiber aligner by image processing and automatic loading system. Optical fiber is indispensable for optical communication systems that transmit large volumes of data at high speed, but super-precision technology in sub-micron units is required for optical axis adjustment, we have developed 6-axis micro stage system for I/O optical fiber arrays, the initial automatic aligning system/software for a input optical array by the image processing technique, fast I/O-synchronous aligning strategy, the automatic loading/unloading system and the automatic UV bonding mechanism. In order to adjust the alignment it used on PC based motion controller, a $10\mu\textrm{mm}$ repeat-detailed drawing of automatic loading system is developed by a primary line up for high detailed drawing. Also, at this researches used the image processing system and algorithm instead of the existing a primary hand-line up. and fiber input array and waveguide chip formed in line by automatic. Therefore, the developed and manufactured optical aligning system in this research fulfills the great role of support industry for major electronics manufacturers, telecommunications companies, universities, government agencies and other research institutions.