• Proceedings of the Korean Society of Precision Engineering Conference
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• 1991.11a
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• pp.87-94
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• 1991

This Paper is to aim the microdefect evaluation of semiconductor Package into a quantitative from NDI's image processing of ultrasonic wave. Accordingly, for the detection of delamination between the Joining condition of boundary microdefect of semiconductor packaga the result from sampling original image, histogramming, binary image or image processing of multinumerloal value is such as the follows. ([) The least limitation from the microdefect detection of the semiconductor package by surveying high ultrasonic wave seems to be about 0.8 $\mu\textrm{m}$ in degree. (2) A result of applying the image processing of multinumerical value to the semiconductor package it was possible to devide the Category into the effectiveness.

• Journal of Industrial Technology
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• v.22 no.B
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• pp.241-249
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• 2002

Optical fiber is indispensable for optical communication systems that transmit large volumes of data at high speed, but super precision technology in sub-micron units is required for optical axis adjustment. We developed the automatic optical fiber by image processing and automatic loading system. we have developed 6-axis micro stage system for I/O optical fiber arrays, the initial automatic aligning system software for a input optical array by the image processing technique, fast I/O-synchronous aligning strategy, the automatic loading/unloading system and the automatic UV bonding mechanism. In order to adjust the alignment it used on PC based motion controller, a $10{\mu}m$ repeat-detailed drawing of automatic loading system is developed by a primary line up for high detailed drawing. Also, at this researches used the image processing system and algorithm instead of the existing a primary hand-line up and fiber input array and waveguide chip formed in line by automatic.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.97-97
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• 2000

In this paper, a signal processing algorithm for software GPS receiver is proposed. The signal processor takes snapshot of the sampled If signal from the RF section of the GPS receiver. All the processing for code and carrier tracking and correlation are implemented using the digital signal processing techniques. In order to achieve fast code acquisition, correlation of the incoming GPS signal is performed using the FFT method, After code acquisition, to reduce the Doppler shift effect and increase the accuracy, the interpolation or the tracking are performed. The performance of the proposed processing algorithm is first evaluated using matlab/simulink. A signal acquisition board for sampling and logging GPS IF signal form the Mitel GPS RF chip set is constructed. In order to analyze the performance of the designed algorithm the experiments are performed and the results are analyzed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.22-30
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• 2009

Due to high levels of integration and complexity, the Network-on-Chip (NoC) approach has emerged as a new design paradigm to overcome on-chip communication issues and data bandwidth limits in conventional SoC(System-on-Chip) design. In particular, exponentially growing of energy consumption caused by high frequency, synchronization and distributing a single global clock signal throughout the chip have become major design bottlenecks. To deal with these issues, a globally asynchronous, locally synchronous (GALS) design combined with low power techniques is considered. Such a design style fits nicely with the concept of voltage-frequency-islands (VFI) which has been recently introduced for achieving fine-grain system-level power management. In this paper, we propose an efficient design methodology that minimizes energy consumption by VFI partitioning on an NoC architecture as well as assigning supply and threshold voltage levels to each VFI. The proposed algorithm which find VFI and appropriate core (or processing element) supply voltage consists of traffic-aware core graph partitioning, communication contention delay-aware tile mapping, power variation-aware core dynamic voltage scaling (DVS), power efficient VFI merging and voltage update on the VFIs Simulation results show that average 10.3% improvement in energy consumption compared to other existing works.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.2
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• pp.55-59
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• 2004

Throughout manufacturing processes, pulse shaping is required for material processing and it is regarded as an important (actor according to the specific characteristics of materials. Therefore, this study suggests a highly appropriate pulse shaping technique using a multi-switching method. This is a pulse superposition method in which one flash lamp can consecutively turn on by the double switching of the discharging system. It is possible to construct a variety of pulse shapes and pulse widths by the consecutive trigger of the silicon-controlled rectifiers (SCR) of a PIC (program integrated circuit) one-chip microprocessor. The use of this technique can provide a number of advantages to people who require suitable pulse shaping for particular applications such as welding, cutting, and drilling.

• ETRI Journal
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• v.27 no.5
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• pp.585-594
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• 2005

A small electronic nose (E-Nose) system has been developed using an 8-channel vapor detection array and personal digital assistant (PDA). The sensor array chip, integrated on a single microheater-embedded polyimide substrate, was made of carbon black-polymer composites with different kinds of polymers and plasticizers. We have successfully classified various volatile organic compounds such as methanol, ethanol, i-propanol, benzene, toluene, n-hexane, n-heptane, and c-hexane with the aid of the sensor array chip, and have evaluated the resolution factors among them, quantitatively. To achieve a PDA-based E-Nose system, we have also elaborated small sensor-interrogating circuits, simple vapor delivery components, and data acquisition and processing programs. As preliminary results show, the miniaturized E-Nose system has demonstrated the identification of essential oils extracted from mint, lavender, and eucalyptus plants.

• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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• 2004.04a
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• pp.275-278
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• 2004

The geo-referencing of satellite imagery is a key task in remote sensing. GCPs are points the position of which is known both in the image and in the supporting maps. Mapping function makes the determination of map coordinates of all image pixels possible. Generally manual operations are done to identify image points corresponding to the points on a digital topographic map. In order to accurately measure ground coordinates of GCPs, differential global positioning system (DGPS) surveying are used. To acquire the sufficient number of well distributed GCPs is one of the most time-consuming and cost-consuming tasks. This paper describes the procedure of automatically extracting GCOs using GCP database. GCP image chips and image matching technique are used for automatic extraction of GCPs. We developed image processing tool for making image chip GCPs and Web Server for management of GCPs.

• ETRI Journal
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• v.35 no.5
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• pp.767-774
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• 2013

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.48-51
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• 1997

This paper presents the algorithm of FIC inspection in chip mounter. When device is mounted on the PCB, it is impossible to get zero defects since there are many problems which can not be predicted. Of these problems, devices with bent corner leads due to mis-handling and which are not placed at a given point measured along the axis are principal problem in SMT(Surface Mounting Technology). In this paper, we proposed a new algorithm based on the Radon transform which uses a projection to inspect the FIC(Flat Integrated Circuit) device and compared this method with other algorithms. We measured the position error and applied this algorithm to our image processing board which is characterized by line scan camera. We compared speed and accuracy in our board.