ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
권호 표지
DOI QR코드

DOI QR Code

A Novel Parallel Viterbi Decoding Scheme for NoC-Based Software-Defined Radio System

  • Wang, Jian (DSP Lab, School of Communication and Information Engineering, University of Electronic Science and Technology of China) ;
  • Li, Yubai (DSP Lab, School of Communication and Information Engineering, University of Electronic Science and Technology of China) ;
  • Li, Huan (DSP Lab, School of Communication and Information Engineering, University of Electronic Science and Technology of China)
  • Received : 2013.01.09
  • Accepted : 2013.04.13
  • Published : 2013.10.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a novel parallel Viterbi decoding scheme is proposed to decrease the decoding latency and power consumption for the software-defined radio (SDR) system. It implements a divide-and-conquer approach by first dividing a block into a series of subblocks, then performing independent Viterbi decoding for each subsequence, and finally merging the surviving subpaths into the final path. Moreover, a network-on-chip-based SDR platform is used to evaluate the performance of the proposed parallel Viterbi decoding scheme. The experiment results show that our scheme can speed up the Viterbi decoding process without increasing the BER, and it performs better than the current state-of-the-art methods.

Keywords

References

  1. A.L.G. Reis et al., "Introduction to the Software-Defined Radio Approach," IEEE Latin America Trans., vol. 10, no. 1, Jan. 2012, pp. 1156-1161. https://doi.org/10.1109/TLA.2012.6142453
  2. P. Suárez-Casal et al., "A Multicore SDR Architecture for Reconfigurable WiMAX Downlink," 13th Euromicro Conf. Dig. Syst. Design: Architectures, Methods, Tools, 2010, pp. 801-804.
  3. G. Fettweis and H. Meyr, "High Speed Parallel Viterbi Decoding: Algorithm and VLSI Architecture," IEEE Commun. Mag., vol. 29, no. 5, May 1991, pp. 46-55.
  4. G. Fettweis, H. Dawid, and H. Meyr, "Minimized Method Viterbi Decoding: 600 Mbit/s per Chip," IEEE GLOBECOM, 1990, pp. 1712-1716.
  5. P.J. Black and T.H.Y. Meng, "A 1-Gb/s, Four-State, Sliding Block Viterbi Decoder," IEEE J. Solid-State Circuits. vol. 32, no. 6, June 1997, pp. 797-805. https://doi.org/10.1109/4.585246
  6. I. Habib, O. Paker, and S. Sawitzki, "Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation," IEEE Trans. Very Large Scale Integr. Syst., vol. 18, no. 5, May 2010, pp. 794-807. https://doi.org/10.1109/TVLSI.2009.2017024
  7. E. Yeo et al., "A 500-Mb/s Soft-Output Viterbi Decoder," IEEE J. Solid-State Circuits, vol. 38, no. 7, July 2003, pp. 1234-1241. https://doi.org/10.1109/JSSC.2003.813250
  8. T. Jarvinen et al., "Systematic Approach for Path Metric Access in Viterbi Decoders," IEEE Trans. Commun., vol. 53, no. 5, May 2005, pp. 755-759. https://doi.org/10.1109/TCOMM.2005.847158
  9. I. Lee and J.L. Sonntag, "A New Architecture for the Fast Viterbi Algorithm," IEEE Trans. Commun., vol. 51, no. 10, Oct. 2003, pp. 1624-1628. https://doi.org/10.1109/TCOMM.2003.818100
  10. J.J. Lai et al., "High Performance Viterbi Decoder on Cell/B.E.," China Commun., vol. 6, no. 2, Apr. 2009, pp. 150-156.
  11. J. Kim, S. Hyeon, and S. Choi, "Implementation of an SDR System Using Graphics Processing Unit," IEEE Commun. Mag., vol. 48, no. 3, Mar. 2010, pp. 156-162.
  12. C.S. Lin et al., "A Tiling-Scheme Viterbi Decoder in Software Defined Radio for GPUs," 7th Int. Conf. Wireless Commun., Netw. Mobile Comput., 2011, pp. 1-4.
  13. W. Plishker et al., "Applying Graphics Processor Acceleration in a Software Defined Radio Prototyping Environment," 22nd IEEE Int. Symp. Rapid Syst. Prototyping, May 2011, pp. 67-73.
  14. T. Nylanden et al., "A GPU Implementation for Two MIMO-OFDM Detectors," Int. Conf. Embedded Comput. Syst., July 2010, pp. 293-300.
  15. F. Clermidy et al., "A 477mW NoC-Based Digital Baseband for MIMO 4G SDR," IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2010, pp. 278-279.
  16. G. Schelle, J. Fifield, and D. Grunwald "A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects," Int. Conf. Field Programmable Logic Appl., 2007, pp. 177-182.
  17. J.H. Bahn, J. Yang, and N. Bagherzadeh, "Parallel FFT Algorithms on Network-on-Chips," 5th Int. Conf. Inf. Technol.: New Generations, 2008, pp. 1087-1093.
  18. L.M. Ni and P.K. McKinley, "A Survey of Wormhole Routing Techniques in Direct Networks," Comput., vol. 26, no. 2, Feb. 1993, pp. 62-76.
  19. R.Y. Shao, S. Lin, and M.P.C. Fossorier, "Two Decoding Algorithms for Tailbiting Codes," IEEE Trans. Commun., vol. 51, no. 10. Oct. 2003, pp. 1658-1665. https://doi.org/10.1109/TCOMM.2003.818084
  20. ETSI, "Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access, Multiplexing and Channel Coding (release 10)," 3GPP TS 36.212 V10.0.0, 2010.
  21. S. Li et al., "McPAT: An Integrated Power, Area, and Timing Modeling Framework for Multicore and Manycore Architectures," Proc. 42nd Annual IEEE/ACM Int. Symp. Microarchitecture, 2009, pp. 469-480.
  22. A.B. Kahng et al., "ORION 2.0: A Power-Area Simulator for Interconnection Networks," IEEE Trans. Very Large Scale Integr. Syst., vol. 20, no. 1, Jan. 2012, pp. 191-196. https://doi.org/10.1109/TVLSI.2010.2091686

Cited by

  1. An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture vol.65, pp.10, 2013, https://doi.org/10.1109/tcsi.2018.2825362