• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.11a
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• pp.388-389
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. However, if software-based method employing GPU is used for AI applications, there is a problem that we can not change the internal circuit of processing unit. In this method, if high-level jobs are required for AI system, we need high-performance GPU, therefore, we have to change GPU or graphic card to perform the jobs. In this work, we developed a CNN-based FPGA (Field Programmable Gate Array) chip to solve this problem.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.1
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• pp.55-62
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• 2016

In this paper, we propose a hybrid multi.system-on-chip (H-MSoC) architecture that provides a high-flexibility system in a rapid development time. The H-MSoC approach provides a flexible system-on-chip (SoC) architecture that is easy to configure for physical- and application-layer development. The physical- and application-layer aspects are dynamically designed and modified; hence, it is important to consider a design methodology that supports rapid SoC development. Physical layer development refers to intellectual property cores or other modular hardware (HW) development, while application layer development refers to user interface or application software (SW) development. H-MSoC is built from multi-SoC architectures in which each SoC is localized and specified based on its development focus, either physical or application (hybrid). Physical HW development SoC is referred to as physical-SoC (Phy-SoC) and application SW development SoC is referred to as application-SoC (App-SoC). Phy-SoC and App-SoC are connected to each other via Ethernet. Ethernet was chosen because of its flexibility, high speed, and easy configuration. For prototyping, we used a LEON3 SoC as the Phy-SoC and a ZYNQ-7000 SoC as the App-SoC. The proposed design was proven in real-time tests and achieved good performance.

• The Journal of the Acoustical Society of Korea
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• v.15 no.6
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• pp.16-25
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• 1996

In this paper, we designed the chip which can classify the Korean characters using CAM(Content Addressable Memory). A high-speed OCR has been implemented by software to recognize the characters. However, it is difficult to process in real-time. The pipelined hardware implementation is one of the solution to recognize the characters in real-time by using the parallel processing techniques. We used the CAM which has the function of high-speed parallel-match to implement easily and twenty reference patterns are used for comparison. The chip has been evaluated result using DLAB of DAZIX. The simulation results have shown that the process speed was $1.6{\mu}s$ per character. Also, we programed using C-language and compared the results.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.505-513
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• 2017

As mobile systems are performing various functionality in the IoT (Internet of Things) era, network-on-chip (NoC) plays a pivotal role to support communication between the tens and in the future potentially hundreds of interacting modules in system-on-chips (SoCs). Owing to intensive research efforts more than a decade, NoCs are now widely adopted in various SoC designs. Especially, studies on application-specific NoCs (ASNoCs) that consider the heterogeneous nature of modern SoCs contribute a significant share to use of NoCs in actual SoCs, i.e., ASNoC connects non-uniform processing units, memory, and other intellectual properties (IPs) using flexible router positions and communication paths. Although it is not difficult to find the prior works on ASNoC synthesis and optimization, little research has addressed the issues how to convert different protocols and data widths to make a NoC compatible with various IPs. Thus, in this paper, we address important issues on ASNoC implementation to support and convert multiple interfaces. Based on the in-depth discussions, we finally introduce our FPGA-proven full-custom ASNoC.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.2
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• pp.71-76
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• 2016

A controller area network (CAN) receiver measures differential voltage on a bus to determine the bus level. Since 3.3V transceivers generate the same differential voltage as 5V transceivers (usually ${\geq}1.5V$), all transceivers on the bus (regardless of supply voltage) can decipher the message. In fact, the other transceivers cannot even determine or show that there is anything different about the differential voltage levels. A new CMOS RC oscillator insensitive supply voltage for clock generation in a CAN transceiver was fabricated and tested to compensate for this drawback in CAN communication. The system consists of a symmetrical circuit for voltage and current switches, two capacitors, two comparators, and an RS flip-flop. The operational principle is similar to a bistable multivibrator but the oscillation frequency can also be controlled via a bias current and reference voltage. The chip test experimental results show that oscillation frequency and power dissipation are 500 kHz and 5.48 mW, respectively at a supply voltage of 3.3 V. The chip, chip area is $0.021mm^2$, is fabricated with $0.18{\mu}m$ CMOS technology from SK hynix.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.10
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• pp.903-910
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• 2000

In this paper, we describe a slave chip based on the Profibus-DP protocol and a system board to verify the developed slave chip. The Profibus-DP protocol is designed using VHDL and implemented on FPGA. The system board adopting the developed FPGA is designed FPGA is designed in which the firmware is implemented on Intel 8051 by using C language. Among the Profibus-DP protocols, low level layers from the physical layer to the data link layer is implemented in the form of hardware that we are able to greatly reduce the CPU load in processing protocols, and then higher layers could be processed by software. These technologies result in an IP to make terminal devices in the distributed control systems. Therefore, many digital logics as well as communication logics can be implemented onto SOC(System On a Chip) and it could be applied to various fieldbus-related areas.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.7
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• pp.513-518
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• 2016

The piezoelectric actuating device is known for its large power density and simple structure. It can generate a larger force than a conventional actuator and has also wide bandwidth with fast response in a compact size. To control the piezoelectric actuator, we need an analog signal conditioning circuit as well as digital microcontrollers. Conventional microcontrollers are not equipped with an analog part and need digital-to-analog converters, which makes the system bulky compared with the small size of piezoelectric devices. To overcome these weaknesses, we are developing a single-chip controller that can handle analog and digital signals simultaneously using mixed-signal FPGA technology. This gives more flexibility than traditional fixed-function microcontrollers, and the control speed can be increased greatly due to the parallel processing characteristics of the FPGA. In this paper, we developed a floating-point multiplier, PWM generator, 80-kHz power control loop, and 1-kHz position feedback control loop using a single mixed-signal FPGA. It takes only 50 ns for single floating-point multiplication. The PWM generator gives two outputs to control the charging and discharging of the high-voltage output capacitor. Through experimentation and simulation, it is demonstrated that the designed control loops work properly in a real environment.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.10
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• pp.21-31
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• 1994

This paper describes the multichannel combined R2MFC/DTMF/CCT reciver which provides a signaling service functions for call processing control in digital switching system. Using the TMS320C25 DSP chip, we have implemented multi-function receriver shich processes 8 channels of R2MFC, DTMF, and CCT signals simultaneously. In order to increase the channel multiplicity of the combined receiver. R2MFC and CCT receiver were employed by discrete Fourier transform(DFT) method using Goertzel algorithm, and DTMFreceiver was employ by infinite impulse reponse(IIR) filtering method using 4KHz subsampling technique. The combined receiver has 4 function modes for each channel such as R2MFC, DTMF, CCT, and Idle modes. The function mode of each channel may be selected at any time by single-chip micro-controller(.mu.C). Hence, the number of channels assigned for each function mode can be adjusted dynamically according to the signaling traffic variations. From the experimental test results using the test-bed, it has been proved that the combined receiver statisfies all receiver satisfies all receiver specifications, and provides good channel multiplicity and performance, Therefore, it may give a great improvement than existing receiver in cost, reliability, availability, and serviceability.

• The KIPS Transactions:PartA
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• v.13A no.7 s.104
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• pp.589-598
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• 2006

In this paper, we describe the development and optimization of an embedded Biuetooth solution on an SoC platform for real-time audio streaming over a Bluetooth wireless link. The solution includes embedded Bluetooth protocol stack and profile simplemented on a virtual operating system for portability, and other optimization techniques to fully exploit the benefits of multimedia-oriented SoC. The optimization techniques implemented in this paper are memory access minimization by using on-chip scratch pad memory, codec library optimization with DSP and parallel memory access instruction set, and dynamic audio quality adjustment regarding current wireless link status. Experimental results show that the optimized solution presented in this paper can support high-qualify audio streaming without the support of external memory.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.6
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• pp.104-110
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• 1994

We proposed a high speed feature extraction algorithm and developed a feature vector extraction chip for high speed character recognition. It is hard to implement a high speed OCR by software alone with statistical method . Thus, the whole recognition process is divided into functional steps, then pipeline processed so that high speed processing is possible with temporal parallelism of the steps. In this paper we discuss the feature extraction step of the functional steps. To extract feature vector, a character image is normalized to 40$\times$40 pixels. Then, it is divided into 5$\times$5 subregions and 4x4 subregions to construct 41 overlapped subregions(10x10 pixels). It requires to execute more than 500 commands to extract a feature vector of a subregion by software. The proposed algorithm, however, requires only 10 cycles since it can extract a feature vector of a columm of subregion in one cycle with array structure. Thus, it is possible to process 12.000 characters per second with the proposed algorithm. The chip is implemented using EPLD and the effectiveness is proved by developing an OCR using it.