• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.838-841
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• 2005

DNA Chip is able to show DNA-Data that includes diseases of sample to User by using complementary characters of DNA. So this paper studied Neural Network algorithm for Image data processing of DNA-chip. DNA chip outputs image data of colors and intensities of lights when some sample DNA is putted on DNA-chip, and we can classify pattern of these image data on user pc environment through artificial neural network and some of image processing algorithms. Ultimate aim is developing of pattern classifying algorithm, simulating this algorithm and so getting information of one's diseases through applying this algorithm. Namely, this paper study artificial neural network algorithm for classifying pattern of image data that is obtained from DNA-chip. And, by using histogram, gradient edge, ANN and learning algorithm, we can analyze and classifying pattern of this DNA-chip image data. so we are able to monitor, and simulating this algorithm.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2005년도 ISMP
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• pp.89-110
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• 2005

A new 3D integration technology using wafer-to-wafer and chip-to-wafer stacking method was described. It was demonstrated that 3D microprocessor, 3D shared memory, 3D image processing chip and 3D artificial retina chip fabricated using 3D integration technology were successfully operated. The possibility of applying 3D image processing chip and 3D artificial retina chip to Robot's eye was investigated. The possibility of implanting 3D artificial retina chip into human eye was investigated.

• 전자공학회논문지C
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• 제34C권10호
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• pp.1-7
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• 1997

This paper proposes a new real-time 2-D convolver filter architecture wihtout using any multiplier. To meet the massive amount of computations for real-time image processing, several commercial 2-D convolver chips have many multipliers occupying large VLSI area. Te proposed architecture using only one shift-and-accumulator can reduce the chip size by more than 70% of commercial 2-D convolver filter chips and can meet the real-time image processing srequirement, i.e., the standard of CCIR601. In addition, the proposed chip can be used for not only 2-D image processing but also 1-D signal processing and has bood scalability for higher speed applications. We have simulated the architecture by using VHDL models and have performed logic synthesis. We used the samsung SOG cell library (KG60K) and verified completely function and timing simulations. The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement, that is, 720*480 pixels per frame and 30 frames per second (10.4 mpixels/second).

• ETRI Journal
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• 제22권1호
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.

• 전자공학회논문지B
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• 제31B권4호
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• Journal of Information Processing Systems
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• 제2권3호
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• pp.189-193
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• 2006

In this study we propose an automatic reading system for diagnostic DNA chips. We define a general specification for an automatic reading system and propose a possible implementation method. The proposed system performs the whole reading process automatically without any user intervention, covering image acquisition, image analysis, and report generation. We applied the system for the automatic report generation of a commercialized DNA chip for cervical cancer detection. The fluorescence image of the hybridization result was acquired with a $GenePix^{TM}$ scanner using its library running in HTML pages. The processing of the acquired image and the report generation were executed by a component object module programmed with Microsoft Visual C++ 6.0. To generate the report document, we made an HWP 2002 document template with marker strings that were supposed to be searched and replaced with the corresponding information such as patient information and diagnosis results. The proposed system generates the report document by reading the template and changing the marker strings with the resultant contents. The system is expected to facilitate the usage of a diagnostic DNA chip for mass screening by the automation of a conventional manual reading process, shortening its processing time, and quantifying the reading criteria.

• 전자공학회논문지A
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• 제31A권10호
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• pp.161-172
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• 1994

This paper describes the design of a neurochip with on-chip learning capability in hardware with multiple processing elements. A digital architecture is adopted because its flexiblity and accuracy is advantageous for simulating the various application systems. The proposed chip consists of several processing elements to fit the large computation of neural networks, and has on-chip learning capability based on error back-propagation algorithm. It also minimizes the number of blobal control signals for processing elements. The modularity of the system makes it possible to buil various kinds of boards to match the expected range of applications.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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• pp.811-815
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• 1990

This paper describes the method on image acquisition and image processing in the turning process. The formation of discontinuous chips during high-speed oblique cutting without lubricant was observed by means of video camera recorder and stroboscope. The image processing technique for chip flow is described and the results are presented for variable feeds. It is concluded that experimental values of chip flow angle are similar to theoretical values of Stabler's rule.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.65-70
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• 2015

In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.

• 한국주조공학회지
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• 제29권1호
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• pp.38-44
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• 2009

Magnetic separation of Fe contaminated Al-Si cutting chip scraps was performed for the recyclability assessment. It was also aimed to investigate the casting and solidification characteristics of the cutting chip scraps. The magnetically separated cutting chip scraps were adequately treated for the casting procedure and test specimens were made into a stepped mold inducing different cooling rates. The test specimens were evaluated by the combined analysis of ICP, Spectroscopy, OM-image analyzer, SEM/EDS, etc. Solidification characteristics of cutting chip scraps were examined as functions of Fe content and cooling rate. It is concluded that the magnetic separation process can be utilized to recycle the Fe contaminated Al-Si cutting chip scraps in the high cooling rate foundry process.