• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.7
• /
• pp.1332-1339
• /
• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.3
• /
• pp.699-707
• /
• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• The KIPS Transactions:PartA
• /
• v.9A no.1
• /
• pp.1-8
• /
• 2002

Most of the traditional embedded web server systems have been designed for monitoring and controlling some dedicated equipments. Hence, not only they have no generality and flexibility but also they are too expensive for the lower-cost domestic equipment. To cope with these difficulty, we suggest a lower-cost ${\mu}$-embedded web server model which is suitable for monitoring and controlling the industry or house equipments by using the internet. The suggested model is based on an one-chip ${\mu}$-processor in which the ISP (In-System Programming) function and flash ROM are embedded basically to minimize the cost of H/W and S/W. Also it allows to add an new function dynamically to provide the generality and flexibility. Finally, to evaluate the feasibility of the suggested model, we have manufactured a test-board based on the ATMega103 ${\mu}$-processor and programmed the control program and tested it on the MS Explorer 5.0 environment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.8
• /
• pp.702-707
• /
• 2002

This paper presents a micro fluxgate sensor in printed circuit board (PCB). The fluxgate sensor consists of five PCB stack layers including one layer magnetic core and four layers of excitation and pick-up coils. The center layer as a magnetic core is made of a micro patterned amorphous magnetic ribbon and the core has a rectangular-ring shape. The amorphous magnetic core is easily saturated due to the low coercive field and closed magnetic path for the excitation field. Four outer layers as an excitation and pick-up coils have a planar solenoid structure. The chip size of the fabricated sensing element is 7.3$\times$5.7$\textrm{mm}^2$. Excellent linear response over the range of -100$\mu$T to +100$\mu$T is obtained with 540V/T sensitivity at excitation square wave of 3 $V_{p-p}$ and 360kHz. The very low power consumption of ~8mW was measured. This magnetic sensing element, which measures the lower fields than 50$\mu$T, is very useful for various applications such as: portable navigation systems, military research, medical research, and space research.h.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2003.11a
• /
• pp.53-58
• /
• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Journal of information and communication convergence engineering
• /
• v.6 no.4
• /
• pp.376-382
• /
• 2008

Developing highly cost-efficient and reliable embedded systems demands hardware/software co-design and co-simulation due to fast TTM and verification issues. So, it is essential that Platform-Based SoC design methodology be used for enhanced reusability. This paper addresses a reusable SoC platform based on OpenCores soft processor with reconfigurable architectures for hardware/software codesign methodology. The platform includes a OpenRISC microprocessor, some basic peripherals and WISHBONE bus and it uses the set of development environment including compiler, assembler, and debugger. The platform is very flexible due to easy configuration through a system configuration file and is reliable because all designed SoC and IPs are verified in the various test environments. Also the platform is prototyped using the Xilinx Spartan3 FPGA development board and is implemented to a single chip using the Magnachip cell library based on $0.18{\mu}m$ 1-poly 6-metal technology.

• 제어로봇시스템학회:학술대회논문집
• /
• 2002.10a
• /
• pp.121.1-121
• /
• 2002

Calculation unit and peripheral units that are used to make the position controller are embedded to one chip FPGA. $\textbullet$ Feed-forward PID controller and interpolator in the calculation unit mitigate frequent context switching. $\textbullet$ The peripheral units reduce the size of the joints position control board. $\textbullet$ Because the calculation unit is designed with pipeline structure, it has the advantages to apply to the multi joints.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.24-30
• /
• 2009

In this paper, the FPGA modem platform complying with 3GPP Release 7 eHSPA specifications and its regularized verification flow are proposed. The FFGA platform consists of modem board supporting physical layer requirements, MCU and DSP core embedded control board to drive the modem board, and peripheral boards for RF interfacing and various equipment interfaces. On the other hand, the proposed verification flow has been regularized into three categories according to the correlation degrees of hardware-software inter-operation, such as simple function test, scenario test call processing and system-level performance test. When it comes to real implementations, the emulation verification strategy for low power mobile SoC is also introduced.

• Korean Journal of Materials Research
• /
• v.19 no.11
• /
• pp.625-630
• /
• 2009

Embedding of active devices in a printed circuit board has increasingly been adopted as a future electronic technology due to its promotion of high density, high speed and high performance. One responsible technology is to embedded active device into a dielectric substrate with a build-up process, for example a chipin-substrate (CiS) structure. In this study, desmear treatment was performed before Cu metallization on an FR-4 surface in order to improve interfacial adhesion between electroless-plated Cu and FR-4 substrate in Cu via structures in CiS systems. Surface analyses using atomic force microscopy and x-ray photoemission spectroscopy were systematically performed to understand the fundamental adhesion mechanism; results were correlated with peel strength measured by a 90o peel test. Interfacial bonding mechanism between electrolessplated Cu and FR-4 substrate seems to be dominated by a chemical bonding effect resulting from the selective activation of chemical bonding between carbon and oxygen through a rearrangement of C-C bonding rather than from a mechanical interlocking effect. In fact, desmear wet treatment could result in extensive degradation of FR-4 cohesive strength when compared to dry surface-treated Cu/FR-4 structures.

• Smart Structures and Systems
• /
• v.6 no.5_6
• /
• pp.689-709
• /
• 2010

In this paper, a low cost, low power but multifunctional wireless sensor node is presented for the impedance-based SHM using piezoelectric sensors. Firstly, a miniaturized impedance measuring chip device is utilized for low cost and low power structural excitation/sensing. Then, structural damage detection/sensor self-diagnosis algorithms are embedded on the on-board microcontroller. This sensor node uses the power harvested from the solar energy to measure and analyze the impedance data. Simultaneously it monitors temperature on the structure near the piezoelectric sensor and battery power consumption. The wireless sensor node is based on the TinyOS platform for operation, and users can take MATLAB$^{(R)}$ interface for the control of the sensor node through serial communication. In order to validate the performance of this multifunctional wireless impedance sensor node, a series of experimental studies have been carried out for detecting loose bolts and crack damages on lab-scale steel structural members as well as on real steel bridge and building structures. It has been found that the proposed sensor nodes can be effectively used for local wireless health monitoring of structural components and for constructing a low-cost and multifunctional SHM system as "place and forget" wireless sensors.