• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.178-182
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• 2003

This paper presents the embedded inductors in PCB (Printed Circuit Board) for PAM(Power Amplifier Module) of mobile terminations. The inductors are designed, simulated, and compared to conventional chip inductors. The Quality factor(Q) and self-resonance frequency(SRF) of the inductors are evaluated. The quality factors of the inductors are two times higher than those of the chip inductors, and the self-resonance frequency is 1.3 times higher than those of chip inductors at the inductance of 2.7 nH and 3.3 nH respectively.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.388-390
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• 2004

In this paper, we performed the implementation of image transmission server system using embedded system that is for the specified object and easy to install at any places and move to wherever. Since the embedded system has lower capability than PC, we have to reduce the quantity of calculation and transmission. The image compression like JPEG, needs that the server calculates for making compressed image, makes the server carry the load. So we compresses the image at the server and transmit the codes to the clients connected, then the received codes from server are decoded and displayed at the clients. In this process to make the image compression and transmission effectively, we decrease the procedure as simple as possible to transmit the data in almost real-time. We used the Redhat linux 9.0 OS at the host PC and the target board based on embedded linux. The image sequences are obtained from the camera attached to the FPGA board with ALTERA chip. For effectiveness and avoiding some constraints, we made the device driver. Generally the image transmission server is PC, but using the embedded system as a server makes the server portable and cheaper than the system based on PC.

• Journal of IKEEE
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• v.22 no.4
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• pp.1214-1217
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• 2018

In this paper, we propose the development of a Small $360^{\circ}$ Oral Scanner embedded board. The proposed small $360^{\circ}$ oral scanner embedded board consists of image level and transfer method changing part FPGA part, memory part and FIFO to USB transfer part. The image level and transmission mode change unit divides the MIPI format oral image received through the small $360^{\circ}$ oral cavity image sensor and the image sensor into low power signal mode and high speed signal mode and distributes them to the port and transfers the level shift to the FPGA unit. The FPGA unit performs functions such as $360^{\circ}$ image distortion correction, image correction, image processing, and image compression. In the FIFO to USB transfer section, the RAW data transferred through the FIFO in the FPGA is transferred to the PC using USB 3.0, USB 3.1, etc. using the transceiver chip. In order to evaluate the efficiency of the proposed small $360^{\circ}$ oral scanner embedded board, it has been tested by an authorized testing institute. As a result, the frame rate per second is over 60 fps and the data transfer rate is 4.99 Gb/second

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.185-191
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• 2006

DSRC((Dedicated Short Range Communication) is dedicated short range communication for wireless communications between RSE(Road Side Equipment) and OBE(On-Board Unit) within vehicle moving high speed. In this paper, we implemented 5.8GHz DSRC modem according to Korea TTA(Telecommunication Technology Association) standard and investigated implementation results and design process for SoC(System on a Chip) embedding ARM CPU which control overall signal and process arithmetic work. The SoC is implemented by 0.11um design technology and 480pins EPBGA package. In the implemented SoC ($Jaguar^{TM}$), 5.8GHz DSRC PHY(Physical Layer) modem and MAC are designed and included. For CPU core ARM926EJ-S is embedded, and LCD controller, smart card controller, ethernet MAC, and memory controller are designed as main function.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.1-7
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• 2021

In this paper, by embedding a bare-die chip-type drive amplifier into the PCB composed of ABF and FR-4, it implements an embedded active device that can be applied in 28 GHz band modules. The ABF has a dielectric constant of 3.2 and a dielectric loss of 0.016. The FR-4 where the drive amplifier is embedded has a dielectric constant of 3.5 and a dielectric loss of 0.02. The proposed embedded module is processed into two structures, and S-parameter properties are confirmed with measurements. The two process structures are an embedding structure of face-up and an embedding structure of face-down. The fabricated module is measured on a designed test board using Taconic's TLY-5A(dielectric constant : 2.17, dielectric loss : 0.0002). The PCB which embedded into the face-down expected better gain performance due to shorter interconnection-line from the RF pad of the Bear-die chip to the pattern of formed layer. But it is verified that the ground at the bottom of the bear-die chip is grounded Through via, resulting in an oscillation. On the other hand, the face-up structure has a stable gain characteristic of more than 10 dB from 25 GHz to 30 GHz, with a gain of 12.32 dB at the center frequency of 28 GHz. The output characteristics of module embedded into the face-up structure are measured using signal generator and spectrum analyzer. When the input power (P_in) of the signal generator was applied from -10 dBm to 20 dBm, the gain compression point (P_1dB) of the embedded module was 20.38 dB. Ultimately, the bare-die chip used in this paper was verified through measurement that the oscillation is improved according to the grounding methods when embedding in a PCB. Thus, the module embedded into the face-up structure will be able to be properly used for communication modules in millimeter wave bands.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.313-316
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• 2002

This paper presents the design and implementation of a crypto processor, a special-purpose microprocessor optimized for the execution of cryptography algorithms. This crypto processor can be used fur various security applications such as storage devices, embedded systems, network routers, etc. The crypto processor consists of a 32-bit RISC processor block and a coprocessor block dedicated to the SEED and triple-DES (data encryption standard) symmetric key crypto (cryptography) algorithms. The crypto processor has been designed and fabricated as a single VLSI chip using 0.5 $\mu\textrm{m}$ CMOS technology. To test and demonstrate the capabilities of this chip, a custom board providing real-time data security for a data storage device has been developed. Testing results show that the crypto processor operates correctly at a working frequency of 30MHz and a bandwidth o1240Mbps.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.106-111
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• 2020

In this paper, we propose the non-contact gesture recognition system and algorithm using proximity-based sensors. The system uses four IR receiving photodiode embedded on a single chip and an IR LED for small area. The goal of this paper is to use the proposed algorithm to solve the problem associated with bringing the four IR receivers close to each other and to implement a gesture sensor capable of recognizing eight directional gestures from a distance of 10cm and above. The proposed system was implemented on a FPGA board using Verilog HDL with Android host board. As a result of the implementation, a 2-D swipe gesture of fingers and palms of 3cm and 15cm width was recognized, and a recognition rate of more than 97% was achieved under various conditions. The proposed system is a low-power and non-contact HMI system that recognizes a simple but accurate motion. It can be used as an auxiliary interface to use simple functions such as calls, music, and games for portable devices using batteries.

• Journal of Broadcast Engineering
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• v.25 no.2
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• pp.200-207
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• 2020

Recently, deep neural networks such as CNN are showing excellent performance in various fields such as image classification, object recognition, visual quality enhancement, etc. However, as the model size and computational complexity of deep learning models for most applications increases, it is hard to apply neural networks to IoT and mobile environments. Therefore, neural network compression algorithms for reducing the model size while keeping the performance have been being studied. In this paper, we apply few compression methods to CNN models and evaluate their performances in the embedded environment. For evaluate the performance, the classification performance and inference time of the original CNN models and the compressed CNN models on the image inputted by the camera are evaluated in the embedded board equipped with QCS605, which is a customized AI chip. In this paper, a few CNN models of MobileNetV2, ResNet50, and VGG-16 are compressed by applying the methods of pruning and matrix decomposition. The experimental results show that the compressed models give not only the model size reduction of 1.3~11.2 times at a classification performance loss of less than 2% compared to the original model, but also the inference time reduction of 1.2~2.21 times, and the memory reduction of 1.2~3.8 times in the embedded board.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1066-1070
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• 2003

Recently technologies have created new principle and theory but the PID control system remains its popularity as the PID controller contains simple structure, including maintenance and parameter adjustment being so simple. Thus, this paper proposes auto tune PID by fuzzy logic controller based on FPGA which to achieve real time and small size circuit board. The digital PID controller design to consist of analog to digital converter which use chip TDA8763AM/3 (10 bit high-speed low power ADC), digital to analog converter which use two chip DAC08 (8 bit digital to analog converters) and fuzzy logic tune digital PID processor embedded on chip FPGA XC2S50-5tq-144. The digital PID processor was designed by fundamental PID equation which architectures including multiplier, adder, subtracter and some other logic gate. The fuzzy logic tune digital PID was designed by look up table (LUT) method which data storage into ROM refer from trial and error process. The digital PID processor verified behavior by the application program ModelSimXE. The result of simulation when input is units step and vary controller gain ($K_p$, $K_i$ and $K_d$) are similarity with theory of PID and maximum execution time is 150 ns/action at frequency are 30 MHz. The fuzzy logic tune digital PID controller based on FPGA was verified by control model of level control system which can control level into model are correctly and rapidly. Finally, this design use small size circuit board and very faster than computer and microcontroller.

• Journal of IKEEE
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• v.21 no.4
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• pp.358-367
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• 2017

Advanced Driver Assistance Systems(ADAS), such as Front Collision Warning System (FCWS) are currently being developed. FCWS require high processing speed because it must operate in real time while driving. In addition, a low-power system is required to operate in an automobile embedded system. In this paper, FCWS is implemented in CPU-FPGA architecture in embedded system to enable real-time processing. The lane detection enabled the use of the Inverse Transform Perspective (IPM) and sliding window methods to operate at fast speed. To detect the vehicle, a Convolutional Neural Network (CNN) with high recognition rate and accelerated by parallel processing in FPGA is used. The proposed architecture was verified using Intel FPGA Cyclone V SoC(System on Chip) with ARM-Core A9 which operates in low power and on-board FPGA. The performance of FCWS in HD resolution is 44FPS, which is real time, and energy efficiency is about 3.33 times higher than that of high performance PC enviroment.