• 한국정보통신학회논문지
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• 제24권5호
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2009년도 정보통신설비 학술대회
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• pp.121-124
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• 2009

In this paper, the techniques and design focus of flexible gain coltrol of LAN(Low Noise Amplifier) using the TSMC 0.18um CMOS process. The design frequency set up a standard on 2.4GHz that is used in Zigbee system. The design concepts a basic Cascode LNA techniques and a swiching circuit consisted of 4 NMOS of load resistance, which convert the output impedenceby tuning on or off. The result show the gain change by NMOS operated swich. The simulation result is that Gain is 14.07dB-16.79dB and NF(Noise Figure) is 1.06dB-1.09dB.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.

• 한국정보기술학회 영문논문지
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• 제10권1호
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• pp.37-43
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• 2020

This paper presents analysis of passive metal interconnection of the LNA block in CMOS integrated circuit. The performance of circuit is affected by the geometry of RF signal path. To investigate the effect of interconnection lines, a cascode LNA is designed, and circuit simulations with full-wave electromagnetic (EM) simulations are executed for different positions of a component. As the results, the position of an external capacitor (C_ex) changes the parasitic capacitance of electric coupling; the placement of component affects the circuit performance. This analysis of interconnection line is helpful to analyze the amount of electromagnetic coupling between the lines, and useful to choose the signal path in the layout design. The target of this work is the RF LNA enabling the seamless connection of wireless data network and the following standards have to be supported in multi-band (WCDMA: 2.11~ 2.17 GHz, CDMA200 1x : 1.84~1.87 GHz, WiBro : 2.3~2.4GHz) mobile application. This work has been simulated and verified by Cadence spectre RF tool and Ansoft HFSS. And also, this work has been implemented in a 0.13um RF CMOS technology process.

• 한국통신학회논문지
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• 제29권6A호
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• pp.697-704
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• 2004

본 논문에서 0.5$\mu\textrm{m}$ GaAs MESFET을 이용하여 5GHz대 무선랜에 사용 가능한 MMIC 가변이득 저잡음 증폭기를 설계 및 제작하였다. 이득과 잡음성능이 우수한 증가형 GaAs MESFET과 선형성이 좋은 공핍형 MESFET 조합의 캐스코드 구조로 저잡음 증폭기를 설계하기 위하여 Turlington의 점근선법을 이용하여 MESFET의 비선형 전류 전압특성에 대한 거동 모델 방정식을 도출하였다. 이로부터 캐스코드 증폭기의 공통 소오스 FET는 4${\times}$50$\mu\textrm{m}$ 크기의 증가형 MESFET으로 공통 게이트 FET는 2${\times}$50$\mu\textrm{m}$ 크기의 공핍형 MESFET으로 설계하였다. 제작된 가변이득 저잡음 증폭기의 잡음지수는 4.9GHz에서 2.4dB, 가변 이득범위는 17dB이상, IIP3는 -4.8dBm이며, 12.8mW의 전력을 소비하였다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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• pp.35-38
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• 2008

In this paper, study noise performance of LNA to enhance Q-factor of input circuit by patterned ground shield is inserted inductor using TSMC 0.18um. Applied LNA technology is cascode method. The input matching circuit was constituted on-chip and wirebonding inductor. Taguchi's method is used for the best suited structure of PGS. We confirmed enhancement of Q-factor by inserted PGS into inductor. The input matching circuit enhanced Q-factor by inductor with PGS improve noise figure of LNA.

• 한국정보통신학회논문지
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• 제7권1호
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• pp.106-113
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• 2003

본 논문에서는 CMOS 기술을 이용하여 2.4GHz ISM 주파수 대역의 LNA를 설계하였다. 캐스코드 증폭기를 이용하여 잡음을 억제하고 이득을 향상시켰으며 캐스캐이드의 공통 소스 증폭기의 출력을 캐스코드와 병렬로 연결되는 MOS의 입력으로 연결하여 IM3를 감소시키고자 하였다. 제안된 저잡음증폭기는 3.3V의 전원을 공급하는 Hynix 0.35$\mu\textrm{m}$ 2-poly 4-metal CMOS 공정을 이용하여 설계되었다. HSPICE Tool을 이용하여 시뮬레이션 하여 13dB의 이득과 1.7dB의 잡음지수, 약 8dBm의 IIP3, -3ldB와 -28dB의 입ㆍ출력 매칭특성을 확인하였다. 이 때 reverse isolation은 -25dB, 전력사용은 4.7mW이었다. Mentor를 이용한 Layout은 2${\times}$2$\mu\textrm{m}$ 이하의 크기를 갖는다.

• 한국멀티미디어학회논문지
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• 제6권1호
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• pp.161-166
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• 2003

본 논문에서는 블루투스에서 사용할 0.25$\mu\textrm{m}$ CMOS 공정을 이용한 고이득 저잡음 증폭기를 설계하였다. 설계한 저잡음 증폭기는 캐스코드 인버터를 이용하였으며, 레퍼런스 전압원을 가지고 쵸크 인덕터를 사용하지 않는 1단으로 설계하였다. 기존 1단으로 설계된 저잡음 증폭기의 10~15dB의 낮은 전력이득을 개선한 구조이다. 설계된 2.4GHz 저잡음 증폭기는 2.2dB의 NF값과 21dB의 높은 전력이득을 가지고 있으며, 2.5V 공급 전원에서 255mW 소모전력을 갖는다

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.443-450
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• 2016

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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• pp.129-132
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• 2000

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.