• 한국정보통신학회논문지
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• 제18권10호
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• pp.2497-2502
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• 2014

본 연구에서는 고주파 마그네트론 스퍼터링 법으로 RF 파워 (50~80 W) 를 변화시켜가며 PES 플라스틱 기판 위에 GZO ($Ga_2O_3$ : 5 wt %, ZnO : 95 wt %) 박막을 제작하여, 광학적 및 전기적 특성을 조사하였다. XRD 측정을 통해 공정 조건에 관계없이 모든 GZO 박막이 c 축으로 우선 성장함을 확인할 수 있었고, 70W에서 제작한 GZO 박막이 반가폭 $0.44^{\circ}$로 가장 우수한 결정성을 나타내었다. 박막의 표면을 AFM 으로 조사한 결과, 표면 거칠기 값은 RF 파워 70 W 에서 제작한 박막에서 가장 낮은 값인 0.20 nm 를 나타내었다. Hall 측정 결과, RF 파워 70 W에서 제작한 GZO 박막에서 가장 낮은 비저항 $6.93{\times}10^{-4}{\Omega}{\cdot}cm$ 값과 가장 높은 캐리어 농도 $7.04{\times}10^{20}cm^{-3}$ 및 이동도 $12.70cm^2/Vs$ 값을 나타내었다. 모든 GZO 박막은 RF 파워에 무관하게 가시광 영역에서 약 80 % 정도의 투과율을 나타냈으며, 캐리어 농도의 증가에 따라 에너지 밴드갭이 청색 편이 되는 Burstein-Moss 효과도 관찰할 수 있었다.

• 한국응용과학기술학회지
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• 제34권4호
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• pp.705-716
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• 2017

본 연구에서는 0.5, 1.0, 1.5 wt%의 $TiO_2$를 함유하는 인듐-티타늄 수산화물을 졸 및 염기 첨가에 의해 얻었고, $200^{\circ}C$와 $500^{\circ}C$에서 겔화 과정을 통해 ITiO(Indium Titanate Oxide)를 얻었다. $200^{\circ}C$에서 겔화 과정 후 얻어지는 ITiO 입자가 작아서 조밀성이 있는 ITiO 타겟을 제조하였다. 0.5, 1.0, 1.5 wt%의 $TiO_2$를 함유하는 ITiO 타겟을 스퍼터링하여 ITiO 박막을 유리판위에 제작하여 비저항, 전하 이동도, 캐리어 농도를 조사하였다. 이들 박막 중에서 산소 조성이 0.4 %인 조건에서 0.5 wt% 중량% $TiO_2$를 함유하는 ITiO 타겟으로부터 제작된 ITiO 박막이 가장 낮은 비저항, 가장 큰 전하이동도 및 가장 낮은 캐리어 농도를 보임을 알 수 있었고, 얻어진 ITiO 박막의 광투과율을 측정하여 적외선 영역에서 광투과율이 ITO(Indium Tin Oxide) 박막에 비해 현저히 증가함을 발견하였다.

• 한국진공학회지
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• 제12권3호
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• pp.168-173
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• 2003

유리 기판 위에 증착된 비정질 실리콘 박막의 고상 결정화에 대한 새로운 방법을 제시하였다. 비정질 실리콘 박막의 하부에 패턴 된 다양한 크기의 $TiSi_2$ 박막을 전기저항 가열 방식으로 가열함으로서 비정질 실리콘이 고상 결정화 되도록 하였다. 박막히터를 이용한 열처리는 매우 빠른 열처리 공정으로써, 일반적인 로에 의한 열처리에 비해 매우 낮은 thermal budget을 가지므로, 유리기판 위에서도 고온 열처리가 가능하다는 장점을 가진다. 본 연구에서는 500 $\AA$의 비정질 실리콘 박막을 약 $850^{\circ}C$ 이상의 높은 온도에서 수 초 내에 결정화 할 수 있음을 보였으며, 열처리 조건의 변화에 따른 영향과 지역선택성의 장점을 보였다.

• 센서학회지
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• 제6권1호
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• pp.49-55
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• 1997

스퍼터링 방법에 의하여 유리 기판위에 ZnO 박막을 형성하여 증착막의 전기, 광학적 특성을 조사하였다. 실온에서 180 W의 고주파 전력과 $1{\times}10^{-3}$ Torr의 스퍼터링 압력일 때 증착된 박막에서 가장 강한 c축 배향성과 가장 낮은 저항률 값($1{\times}10^{-4}{\Omega}{\cdot}cm$)을 나타내었고, 이 때의 캐리어 농도 및 홀 이동도는 각각 $6.27{\times}10^{20}cm^{-3}$와 $22.04cm^{2}/V{\cdot}s$이었다. 증착된 ZnO 박막의 가시광 투과율은 90% 이상을 나타내었으며 330 nm 이하의 자외선 영역과 830 nm 이상의 적외선 영역에서는 뛰어난 광 차단 효과를 나타내었다. 또한 증착된 박막을 수소 분위기에서 열처리함으로써 저항률이 감소하였고, 안정된 박막을 얻을 수 있었다.

• 마이크로전자및패키징학회지
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• 제25권2호
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• pp.49-53
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• 2018

최근 유연 소자, 투명 소자, MEMS 소자와 같은 다양한 소자를 결합하는 시스템 집적화 기술이 많이 개발되고 있다. 이러한 다종 소자 시스템 제조 기술의 핵심 공정은 칩 또는 웨이퍼 레벨의 접합 공정, 기판 연삭 공정, 그리고 박막 기판 핸들링 기술이라 하겠다. 본 연구에서는 Si 기판 연삭 공정이 투명 박막 트랜지스터나 유연 전극 소재로 적용되는 산화주석 박막의 전기적 성질에 미치는 영향을 분석하였다. Si 기판의 두께가 얇아질수록 Si d-spacing은 감소하였고, Si 격자 내에 strain이 발생하였다. 또한, Si 기판의 두께가 얇아질수록 산화주석 박막 내 캐리어 농도가 감소하여 전기전도도가 감소하였다. 얇은 산화 주석 박막의 경우 전기전도도는 두꺼운 산화 주석 박막보다 낮았으며 Si 기판의 두께에 의해 크게 변하지 않았다.

• Transactions on Electrical and Electronic Materials
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• 제12권2호
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• pp.56-59
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• 2011

The characterization of the chemical mechanical polishing (CMP) process for undensified phophosilicate glass (PSG) film is reported using design of experiments (DOE). DOE has been used by experimenters to understand the relationship between the input variables and responses of interest in a simple and efficient way, and it typically is beneficial for determining the appropriatesize of experiments with multiple process variables and making statistical inferences for the responses of interest. The equipment controllable parameters used to operate the machine consist of the down force of the wafer carrier, pressure on the back side wafer, table and spindle speeds (SS), slurry flow (SF) rate, pad condition, etc. None of these are independent ofeach other and, thus, the interaction between the parameters also needs to be understoodfor improved process characterization in CMP. In this study, we selected the five controllable equipment parameters the most recommendedby process engineers, viz. the down force (DF), back pressure (BP), table speed (TS), SS, and SF, for the characterization of the CMP process with respect to the material removal rate and film uniformity in percentage terms. The polished material is undensified PSG which is widely used for the plananization of multi-layered metal interconnects. By statistical modeling and the analysis of the metrology data acquired from a series of $2^{5-1}$ fractional factorial designs with two center points, we showed that the DF, BP and TS have the greatest effect on both the removal rate and film uniformity, as expected. It is revealed that the film uniformity of the polished PSG film contains two and three-way interactions. Therefore, one can easily infer that process control based on a better understanding of the process is the key to success in current semiconductor manufacturing, in which the size of the wafer is approaching 300 mm and is scheduled to continuously increase up to 450 mm in or slightly after 2012.

• 한국전기전자재료학회논문지
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• 제24권7호
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• pp.568-573
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• 2011

AZO (Al doped ZnO) thin films were deposited on the quartz substrates with thickness variation from 25 to 300 nm by using PLD (pulsed laser deposition). XRD (x-ray diffractometer), SPM (scanning probe microscopy), Hall effect measurement and uv-visible spectrophotometer were employed to investigate the structural, morphological, electrical and optical properties of the thin films. XRD results demonstrated that films were preferrentially oriented along the c-axis and crystallinity of film was improved with increase of film thickness. As for the surface morphologies, the mean diameter and root mean square of grains were increased as the film thickness was increased. When the film thickness was 200 nm, the lowest resistivity of $4.25{\times}10^{-4}\;{\Omega}cm$ obtained with carrier concentration of $6.84{\times}10^{20}\;cm^{-3}$ and mobility of $21.4\;cm^2/V{\cdot}S$. All samples showed more than 80% of transmittance in the visible range. Upon these results, it is found that the samples thickness can affect their structural, morphological, optical and electrical properties. This study suggests that the resistivity can be improved by controlling film thickness.

• Transactions on Electrical and Electronic Materials
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• 제12권3호
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• pp.115-118
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• 2011

Process characterization of the chemical mechanical polishing (CMP) process for undensified phosphosilicate glass (PSG) film is reported using design of experiments (DOE). DOE has been addressed to experimenters to understand the relationship between input variables and responses of interest in a simple and efficient way. It is typically beneficial for determining the adequate size of experiments with multiple process variables and making statistical inferences for the responses of interests. Equipment controllable parameters to operate the machine include the down force (DF) of the wafer carrier, pressure on the backside of the wafer, table and spindle speed (SS), slurry flow rate, and pad condition. None of them is independent; thus, the interaction between parameters also needs to be indicated to improve process characterization in CMP. In this paper, we have selected the five controllable equipment parameters, such as DF, back pressure (BP), table speed (TS), SS, and slurry flow (SF), most process engineers recommend to characterize the CMP process with respect to material removal rate (RR) and film uniformity as a percentage. The polished material is undensified PSG. PSG is widely used for the plananization in multi-layered metal interconnects. We identify the main effect of DF, BP, and TS on both RR and film uniformity, as expected, by the statistical modeling and analysis on the metrology data acquired from a series of $2^{5-1}$ fractional factorial design with two center points. This revealed the film uniformity of the polished PSG film contains two and three-way interactions. Therefore, one can easily infer that the process control based on better understanding of the process is the key to success in semiconductor manufacturing, typically when the wafer size reaches 300 mm and is continuously scheduled to expand up to 450 mm in or little after 2012.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.334-334
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• 2012

Transparent oxide semiconductors have recently attracted much attention as channel layer materials due to advantageous electrical and optical characteristics such as high mobility, high stability, and good transparency. In addition, transparent oxide semiconductor can be fabricated at low temperature with a low production cost and it permits highly uniform devices such as large area displays. A variety of thin film transistors (TFTs) have been studied including ZnO, InZnO, and InGaZnO as the channel layer. Recently, there are many studies for substitution of Ga in InGaZnO TFTs due to their problem, such as stability of devices. In this work, new quaternary compound materials, tantalum-indium-tin oxide (TaInSnO) thin films were fabricated by using co-sputtering and used for the active channel layer in thin film transistors (TFTs). We deposited TaInSnO films in a mixed gas (O2+Ar) atmosphere by co-sputtering from Ta and ITO targets, respectively. The electric characteristics of TaInSnO TFTs and thin films were investigated according to the RF power applied to the $Ta_2O_5$ target. The addition of Ta elements could suppress the formation of oxygen vacancies because of the stronger oxidation tendency of Ta relative to that of In or Sn. Therefore the free carrier density decreased with increasing RF power of $Ta_2O_5$ in TaInSnO thin film. The optimized characteristics of TaInSnO TFT showed an on/off current ratio of $1.4{\times}108$, a threshold voltage of 2.91 V, a field-effect mobility of 2.37 cm2/Vs, and a subthreshold swing of 0.48 V/dec.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.52-52
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• 2018

Only approximately 30% of fossil fuel energy is used; therefore, it is desirable to utilize the huge amounts of waste energy. Thermoelectric (TE) materials that convert heat into electrical power are a promising energy technology. The TE materials can be formed either as thin films or as bulk semiconductors. Generally, thin-film TE materials have low energy conversion rates due to their thinness compared to that in bulk. However, an advantage of a thin-film TE material is that the efficiency can be smartly engineered by controlling the nanostructure and composition. Especially nanostructured TE thin films are useful for mitigating heating problems in highly integrated microelectronic devices by accurately controlling the temperature. Hence, there is a rising interest in thin-film TE devices. These devices have been extensively investigated. It is demonstrated that transparent amorphous oxide semiconductors (TAOS) can be excellent thermoelectric (TE) materials, since their thermal conductivity (${\kappa}$) through a randomly disordered structure is quite low, while their electrical conductivity and carrier mobility (${\mu}$) are high, compared to crystalline semiconductors through the first-principles calculations and the various measurements for the amorphous In-Zn-O (a-IZO) thin film. The calculated phonon dispersion in a-IZO shows non-linear phonon instability, which can prevent the transport of phonon. The a-IZO was measured to have poor ${\kappa}$ and high electrical conductivity compared to crystalline $In_2O_3:Sn$ (c-ITO). These properties show that the TAOS can be an excellent thin-film transparent TE material. It is suggested that the TAOS can be employed to mitigate the heating problem in the transparent display devices.