• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1763-1768
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• 2016

This paper presents the electrical characteristics of the gallium nitride (GaN) current aperture vertical electron transistor (CAVET) by using two-dimensional (2-D) technology computer-aided design (TCAD) simulations. The CAVETs are considered as the alternative device due to their high breakdown voltage and high integration density in the high-power applications. The optimized design for the CAVET focused on the electrical performances according to the different gate-source length ($L_{GS}$) and aperture length ($L_{AP}$). We analyze DC and RF parameters inducing on-state current ($I_{on}$), threshold voltage ($V_t$), breakdown voltage ($V_B$), transconductance ($g_m$), gate capacitance ($C_{gg}$), cut-off frequency ($f_T$), and maximum oscillation frequency ($f_{max}$).

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.112-112
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• 2009

Temperature dependence of the ferroelectric properties of poly(vinylidefluoride-trifluoroethylene) copolymer thin films are studied with various insulators such as $SrTa_2O_6$ and $La_2O_3$. Thin films of poly(vinylidene fluoridetrifluoroethylene) 75/25 copolymer were prepared by chemical solution deposition on p-Si substrate. Capacitance-voltage (C-V) and current density (J-V) behavior of the Au/P(VDF-TrFE)/Insulator/p-Si structures were studied at ($150-200\;^{\circ}C$) and dielectric constant of the each insulators were measured to be about 15 at $850\;^{\circ}C$ for 10 minutes. Memory window width at 5 V bias the MFIS(metal-ferroelectric-insulator-semiconductor) structure with as deposited films was about 0.5 V at high temperature ($200\;^{\circ}C$). And the memory window width increased as voltage increased from 1 V to 5 V.

• E2M - 전기 전자와 첨단 소재
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• 제16권9호
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• pp.63.1-63
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• 2003

Catalytic chemical vapor deposition (Cat-CVD) has been developed to deposit alumina(Al$_2$O$_3$) thin films on silicon (Si) crystal using N$_2$ bubbled tir-methyl aluminium [Al(CH$_3$)$_3$, TMA] and molecular oxygen (O$_2$) as source species and tungsten wires as a catalyzer. The catalyzer dissociated TMA at approximately 600$^{\circ}C$ The maximum deposition rate was 18 nm/min at a catalyzer temperature of 1000 and substrate temperature of 800$^{\circ}C$. Metal oxide semiconductor (MOS) diodes were fabricated using gates composed of 32.5-nm-thick alumina film deposited as a substrate temperature of 400oC. The capacitance measurements resulted in a relatively dielectric constant of 7, 4, fixed charge density of 1.74*10e12/$\textrm{cm}^2$, small hysteresis voltage of 0.12V, and very few interface trapping charge. The leakage current was 5.01*10e-7 A/$\textrm{cm}^2$ at a gate bias of 1V.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제52권4호
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• pp.159-163
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• 2003

ln this work, we studied electrical characteristics and leakage current mechanism of $Ta_2O_{5}$ MOS(Metal-Oxide-Semiconductor) devices. $Ta_2O_{5}$ thin film (63 nm) was deposited by ALD(Atomic Layer Deposition) method at temperature of 235 $^{\circ}C$. The structures of the $Ta_2O_{5}$ thin films were examined by XRD(X-Ray Diffraction). From XRD, it is found that the structure of $Ta_2O_{5}$ is single phase and orthorhombic. From capacitance-voltage (C-V) anaysis, the dielectric constant was 19.4. The temperature dependence of current density-electric field (J-E) characteristics of $Ta_2O_{5}$ thin film was studied at temperature range of 300 - 423 K. In ohmic region (<0.5 MV/cm), the resistivity was 2.456${\times}10^{14}$ ($\omega{\cdot}cm$ at 348 K. The Schottky emission is dominant at lower temperature range from 300 to 323 K and Poole-Frenkel emission is dominant at higher temperature range from 348 to 423 K.

• 한국생산제조학회지
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• 제22권1호
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• pp.77-84
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• 2013

In this paper, we review two-dimensional measuring methods referring to target patterns. The patterns consist of two linearly-repeated patterns or is designed repeatedly in two-dimension. The repeated properties are reflectivity, refractivity, air-gapping distance, capacitance, magnetic reluctance, electrical resistance and sloping gradient, etc. However, the optical methods are generally used for high speed processing and density, and their encoding principles are treated here. In case of two-dimensional pattern, as there is not inherently error between single units encoding the pattern except for the metrology frame errors, the end-effector position of an object accompanying the pattern can be measured with respect of the global frame without via error. Therefore, it is regarded as a substitute for laser interferometer with severe environmental constraints and has been applied to the high-accurate planar actuator.

• 열처리공학회지
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• 제14권3호
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• pp.151-154
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• 2001

$TiO_2$ thin film has wide application because of its high capacitanca, reflection, and good transmissivity in visible range. $TiO_2$ thin film can be made by thermal deposition method, reactive evaporation method, activated reactive evaporation(ARE) method. In the case of thermal deposition, the oxygen deficiency can occur because the melting point of Ti is very high. While in the case of reactive evaporation, high density $TiO_2$ can not be made, because reactive gas($O_2$) and evaporated material(Ti) are not fully combined, activated reactive evaporation, $TiO_2$ is easily deposited at lower gas pressure compared with reactive evaporation because the ionized reactive gas is made by plasma. Therefore, activated reactive evaporation is very useful to deposit the material having the high melting point. In this work, we formed $TiO_2$ thin film by activated reactive evaporation method. The surface of $TiO_2$ thin film was analyzed by X-ray photoelectron spectroscopy. The surface morphology which was analyzed by atomic force microscopy(AFM) shows that feature of the film surface is uniform. The dielectric capacitance, withstanding voltage were $600{\mu}F/cm^2$, 0.4V respectively. In further work, we can increase the withstanding voltage by improving the deposition parameter of substrates.

• 한국재료학회지
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• 제13권11호
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• pp.711-716
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• 2003

Gate length, height, and silicide thickness have all been shrinking linearly as device density has progressively increased over the years. We investigated the effect of the cobalt diffusion during the silicide formation process on the 60$\AA$-thick gate oxide lying underneath the Ti/Co and Co/Ti bilayers. We prepared four different cobalt silicides, which have similar sheet resistance, made from the film structure of Co/Ti(interlayer), and Ti(capping layer)/Co, and peformed the current-voltage, time-to-break down, and capacitance-voltage measurements. Our result revealed that the cobalt silicide process without the Ti capping layer allowed cobalt atoms to diffuse into the upper interface of gate oxides. We propose that 100$\AA$-thick titanium interlayer may lessen the diffusion of cobalt to gate oxides in 1500-$\AA$ height polysilicon gates.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2011년도 추계학술발표대회
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• pp.14-14
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• 2011

AlInN has been studied extensively over the past few years due to its interesting material properties that are not present in other ternary nitrides. However, basic material study of AlInN has not been reported as much compared to device applications due to the difficulty in the growth. We have performed the material studies from various aspects. A secondary ion mass spectrometry (SIMS) has shown high oxygen content above $1{\times}10^{18}\;cm^{-3}$ with its insensitivity to the growth conditions. While the free carrier concentration observed by the capacitance-voltage (C-V) measurements was about $3{\times}10^{17}\;cm^{-3}$, the activation energy measured by temperature dependent C-V was only about 4 meV. Si doped AlInN (Si level ${\sim}2{\times}10^{18}\;cm^{-3}$) showed almost no carrier freeze-out at carrier density of $1{\times}10^{18}\;cm^{-3}$. More studies were carried out with a transmission electron microscopy, time-resolved photoluminescence and other analytical techniques to understand the results from SIMS and C-V studies. In this report, we will discuss the possible correlations between the abnormal characteristics in AlInN.

• 전기학회논문지
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• 제59권6호
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• pp.1095-1102
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• 2010

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. High growth of the flash memory market has been driven by two combined technological efforts that are an aggressive scaling technique which doubles the memory density every year and the introduction of MLC(multi level cell) technology. Therefore, the CCI is a critical factor which affects occurring data errors in cells. We introduced an equation of CCI model and designed an equalizer reducing CCI based on the proposed equation. In the model, we have been considered the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. Also we design and verify the proposed equalizer using Matlab. As the simulation result, the error correction ratio of the equalizer shows about 20% under 20nm NAND process where the memory channel model has serious CCI.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2009년도 춘계학술대회 논문집
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• pp.94-94
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• 2009

최근 실리콘 태양전지는 점점 얇아 지는 추세에 있다. 실리콘 태양전지에 있어 실리콘의 두께를 감소시키는 것은 실리콘 소모량을 줄이는데 있어 필수적인 조건이 되었다. 이에 따라 실리콘 표면의 passivation도 더욱 중요하게 여겨지고 있다. 실리콘 태양전지의 passivation막의 한 종류인 $Al_2O_3$는 다른 산화막 물질들과는 달리 negative fixed charge를 가지고 있고 charge의 양이 다른 산화막의 density보다 높아 p-type 실리콘의 경우 후면 passivation막으로 이용이 고려되고 있다. 본 연구에서는 atomic layer deposition으로 $Al_2O_3$막을 실리콘 위에 증착하여 열처리에 따른 그 특성을 비교하고 태양전지를 제작하였다. $Al_2O_3$막을 rapid thermal annealing을 통해 서로 다른 분위기에서 열처리 한 결과를 capacitance-voltage를 통해 측정하여 비교, 분석하였고 ellipsomety 분석을 통해 광학적 특성을 비교하였다. 또한 열처리 온도의 변화에 따른 $Al_2O_3$내에 charge에 변화가 있다는 것을 관찰하였다. 이러한 charge의 변화가 태양전지의 passivation에 영향을 주는지 관찰하기 위해 Quasi-steady state photoconductace를 통해 lifetime의 변화를 관찰 하였다. 이러한 실험결과로부터 열처리 분위기와 온도를 최적화 하여 태양전지 passivation 특성을 증가시킬 수 있었다.