• 제목/요약/키워드: calibration matching

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The Study of the Geometric Structure Optimization for the Stereo X-ray Inspection System Using the Calibration (Calibration을 통한 스테레오 X-ray 검색장치의 기하구조 최적화 연구)

  • Hwang, Young-Gwan;Lee, Nam-Ho;Lee, Seung-Min;Park, Jong-Won
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.9
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    • pp.3422-3427
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    • 2010
  • In this paper, we presents a sensor calibration technique using stereo X-ray images to provide efficient inspection of fast moving cargo objects. Stereo X-ray scanned images are acquired from a specially designed equipment which consists of a X-ray source, dual-linear array detector, and a conveyor system. Dual detector is installed so that rectified stereo X-ray images of objects are acquired. Using the stereo X-ray images, we carry out a sensor calibration to find the correspondences between the images and reconstruct 3-D shapes of real objects. Using the Image acquired from the stereo detectors with varying distances, we calculated the GCP(ground control point)of the image. And we figure out the error by comparing calculated GCP and GCP of the real object. The experimental results show the proposed technique can enhance the accuracy of stereo matching and give more efficient visualization for cargo inspection image.

A 6-bit 3.3GS/s Current-Steering DAC with Stacked Unit Cell Structure

  • Kim, Si-Nai;Kim, Wan;Lee, Chang-Kyo;Ryu, Seung-Tak
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.3
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    • pp.270-277
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    • 2012
  • This paper presents a new DAC design strategy to achieve a wideband dynamic linearity by increasing the bandwidth of the output impedance. In order to reduce the dominant parasitic capacitance of the conventional matrix structure, all the cells associated with a unit current source and its control are stacked in a single column very closely (stacked unit cell structure). To further reduce the parasitic capacitance, the size of the unit current source is considerably reduced at the sacrifice of matching yield. The degraded matching of the current sources is compensated for by a self-calibration. A prototype 6-bit 3.3-GS/s current-steering full binary DAC was fabricated in a 1P9M 90 nm CMOS process. The DAC shows an SFDR of 36.4 dB at 3.3 GS/s Nyquist input signal. The active area of the DAC occupies only $0.0546mm^2$ (0.21 mm ${\times}$ 0.26 mm).

A Study on the Color Management using sRGB Standard Color Space (sRGB 표준색공간을 이용한 컬러매니지먼트에 관한 연구)

  • Kim, Dong-Koun;Cho, Ga-Ram;Koo, Chul-Whoi
    • Journal of the Korean Graphic Arts Communication Society
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    • v.23 no.1
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    • pp.37-51
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    • 2005
  • The solution way of color difference in display device is using a device profile recorded with color dimension, color properties of each device and is using sRGB color space. The color matching is better sRGB than RGB color space. The sRGB is independent device color space and based on the monitor characteristice. An accurate characterization of the display device is essential for color matching. The calibration and characterization process in display device is needed to transform the device dependent color to the device independent color. The process of characterization performs a linerizaiton and transforms the linearized values into the CIE XYZ tristimulus values. The purposes of this paper is to estimate color reproduction using device profile and to explain the propriety of transformation method using variable.

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The Manufacture of Color Filter for Liquid Crystal Display by Screen Printing Method (Screen인쇄법에 의한 Liquid Crystal Display용 Color Filter 제작)

  • 손세모
    • Journal of the Korean Graphic Arts Communication Society
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    • v.13 no.1
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    • pp.39-55
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    • 1995
  • There has been an enormous emergence of imaging systems dedicated to hardcopy and softcopy color-appearance comparisons. Pre-press industry use the CRT as a soft proofing device to preview and aid with color corrections and changes before producing the final printed image. Color DTP system is required an accurate image-matching between CRT-image and printed image. In other to develop the color DTP,CRT calibration and CRT color transform to CIE color system are necessary. In this paper, we described a method CRT color transform to CIELab color system using RGB image raw data. Experimental results show that described method is useful valid of color image matching.

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Use of dummy antenna to monopole antenna factor (더미 안테나를 사용한 모노폴 안테나 보정계수 추출)

  • 안형배;주은정;이황재;강대현;이종악
    • Proceedings of the IEEK Conference
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    • 2001.06a
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    • pp.169-172
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    • 2001
  • This paper has been studied a calibration techniques for monopole antenna in the frequency range 150 KHz to 30 MHz. The long wavelength associated with the low frequency, methods used to calibrate or characterize antennas at higher frequencies are not applicable. The equivalent capacitance substitution method uses a dummy antenna in place of the actual rod element See figure 1. for guidance in making a dummy antenna. Set up the matching network to be characterized and the measuring equipment as shown in Figure 2. Subtract the measured output of the matching network from the measured output of the signal generator and subtract -6 dB(for the 1 m rod). Measurements made at a sufficient number of frequencies number of frequencies to obtain a smooth curve of antenna factor.(fig 5.)

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3D geometric model generation based on a stereo vision system using random pattern projection (랜덤 패턴 투영을 이용한 스테레오 비전 시스템 기반 3차원 기하모델 생성)

  • Na, Sang-Wook;Son, Jeong-Soo;Park, Hyung-Jun
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 2005.05a
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    • pp.848-853
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    • 2005
  • 3D geometric modeling of an object of interest has been intensively investigated in many fields including CAD/CAM and computer graphics. Traditionally, CAD and geometric modeling tools are widely used to create geometric models that have nearly the same shape of 3D real objects or satisfy designers intent. Recently, with the help of the reverse engineering (RE) technology, we can easily acquire 3D point data from the objects and create 3D geometric models that perfectly fit the scanned data more easily and fast. In this paper, we present 3D geometric model generation based on a stereo vision system (SVS) using random pattern projection. A triangular mesh is considered as the resulting geometric model. In order to obtain reasonable results with the SVS-based geometric model generation, we deal with many steps including camera calibration, stereo matching, scanning from multiple views, noise handling, registration, and triangular mesh generation. To acquire reliable stere matching, we project random patterns onto the object. With experiments using various random patterns, we propose several tips helpful for the quality of the results. Some examples are given to show their usefulness.

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Three Dimension Scanner System Using Parallel Camera Model (패러렐 카메라모델을 이용한 3차원 스캐너 시스템)

  • Lee, Hee-Man
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.38 no.2
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    • pp.27-32
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    • 2001
  • In this paper, the three dimension scanner system employing the parallel camera model is discussed. The camera calibration process and the three dimension scanning algorithm are developed. The laser strip line is utilized for assisting stereo matching. An object being scanned rotates on the plate which is activated by a stepping motor, The world coordinate which is. the measured distance from the camera to the object is converted into the model coordinate. The facets created from the point. cloud of the model coordinate is used for rendering the scanned model by using the graphic library such as OpenGL. The unmatched points having no validate matching points are interpolated from the validate matching points of the vicinity epipolar lines.

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Stereoscopic PIV (스테레오 PIV)

  • Doh, D.H.;Lee, W.J.;Cho, G.R.;Pyun, Y.B.;Kim, D.H.
    • Proceedings of the KSME Conference
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    • 2001.11b
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    • pp.394-399
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    • 2001
  • A new stereoscopic PIV is introduced. The system works with CCD cameras, stereoscopic photogrammetry, and a 3D-PTV principle. Virtual images are produced for the construction of a benchmark testing tool of PIV techniques. The arrangement of the two cameras is based on angular position. The calibration of cameras and the pair-matching of the three-dimensional velocity vectors are based on 3D-PTV technique.

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Bayesian Hypothesis Testing for the Difference of Quantiles in Exponential Models

  • Kang, Sang-Gil
    • Journal of the Korean Data and Information Science Society
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    • v.19 no.4
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    • pp.1379-1390
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    • 2008
  • This article deals with the problem of testing the difference of quantiles in exponential distributions. We propose Bayesian hypothesis testing procedures for the difference of two quantiles under the noninformative prior. The noninformative prior is usually improper which yields a calibration problem that makes the Bayes factor to be defined up to a multiplicative constant. So we propose the objective Bayesian hypothesis testing procedures based on the fractional Bayes factor and the intrinsic Bayes factor under the matching prior. Simulation study and a real data example are provided.

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A Calibration-Free 14b 70MS/s 0.13um CMOS Pipeline A/D Converter with High-Matching 3-D Symmetric Capacitors (높은 정확도의 3차원 대칭 커패시터를 가진 보정기법을 사용하지 않는 14비트 70MS/s 0.13um CMOS 파이프라인 A/D 변환기)

  • Moon, Kyoung-Jun;Lee, Kyung-Hoon;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.12 s.354
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    • pp.55-64
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    • 2006
  • This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.