• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.543-551
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• 2017

SOL (Short, Open and Load) calibration based on iterative error sensitivity is proposed in this paper. With advanced SOL calibration, unknown parasitic parameters at on-chip terminations are accurately estimated up to 20 GHz. Artificial terminations are designed on printed circuit board (PCB) to experiment the proposed method. On-chip SHORT, OPEN and LOAD fabricated inside silicon shows the accuracy of proposed calibration method through the comparison with known fixture S-parameter after de-embedding.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.577-578
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• 2008

This paper proposes new analog ZQ calibration scheme. Proposed analog ZQ calibration scheme is for minimizing the reflection which degrade the signal integrity. And this scheme is for minimizing CIO capacitance. It is simulated under 1.5v supply voltage and samsung 0.18um process. Power consumption of proposed analog ZQ calibration circuit was improved by 32%. Under all skew, temperature from $30^{\circ}C$ to $90^{\circ}C$ and Monte carlo simulation, quantization error of RZQ(=$240{\Omega}$) is less han 1.07%.

• 전자공학회논문지A
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• 제33A권6호
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• pp.230-238
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• 1996

In this paper, digital corrction and calibration circuit for a high-resolution CMOS pipelined A/D converter are proposed. The circuits were actually applied to a 12 -bit 4-stage pipelined A/D converter which was implemented in a 0.8${\mu}$m p-well CMOS process. The proposed digital correction logic is based on optimum multiplexer and two nonoverlapping clock phases resulting in a small die area snd a modular pipelined architecture. The propsoed digital calibration logic which consists of calibration control logic, error averaging logic, and memory can effectively perform self-calibration with little modifying analog functional bolcks of a conventional pipelined A/D conveter.

• 한국항공운항학회지
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• 제11권1호
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• pp.41-55
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• 2003

A calibration jet system using separate blower is developed to calibrate a flow sensor effectively. Designed open circuit type mini calibration jet system, which has the dimension of $0.5m(W){\times}1.17m(H)$ is small compared with conventional calibration jet systems. The exit of nozzle has exchangeable contractions with a cross section area of $38.5cm^2$ , and a cross section area of $113.1cm^2$, respectively. The ranges of wind speed at exit of exchangeable nozzles are $7.5{\sim}42\;m/s$ and $1.8{\sim}16.5\;m/s$, respectively. The input power for the high pressure blower is 1.18kW. The turning vanes for corner was rolled flat plate parallel to the flow direction. The flow conditioning screen was located immediately downstream of the wide-angle diffuser. The honeycomb and two flow conditioning screens were located in the stagnation chamber. From the economical point of view and the simplicity of the calibration jet system set up and handling, it can be said that the developed calibration jet system is an effective calibration jet system. This system can also be used to calibrate the flow sensor with high resolution.

• 대한기계학회논문집B
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• 제25권9호
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• pp.1201-1208
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• 2001

Variable temperature anemometer(VTA) has greater sensitivity than a conventional constant temperature anemometer(CTA). In order to design a reliable VTA system, however, an elaborate photoconductive cell stabilizing circuit which plays a key role in setting wire-overheat ratio should be firstly developed. In this study, a stabilizing circuit which adopts proportional-integral analog controller was proposed and thoroughly tested for its accuracy and reproducibility. In contrast to the available circuit suggested by Takagi, the present circuit has characteristic that the resistance of a photoconductive cell increases with the increase of input voltage, which makes the current circuit very suitable for the design of VTA. Finally, VTA adopting stabilizing circuit was made and the enhanced sensitivity of the VTA was validated experimentally by comparing the calibration curves of VTA and CTA.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 기술교육전문연구회
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• pp.42-46
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• 2003

In this study, to measure the moisture of compaction, it is designed to use the 2neutron detectors. To perform the optimal design of their circuit, it is planned high voltage generator and voltage stable circuit and they are very suitable for detection demand. Also, it can be count to data calibration excluded count of ripple.

• 대한전자공학회논문지SD
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• 제48권4호
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• pp.14-23
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• 2011

본 논문에서는 자체보정 벡터 발생기(Self-Calibrated Vector Generator)를 이용한 7-bit 2GSPS folding/interpolation A/D Converter (ADC)를 제안한다. 제안하는 ADC는 2GSPS 의 고속 변환에 적합한 상위 2-bit, 하위 5-bit 인 분할구조로 설계 되었으며, 각각의 folding/interpolation rate는 4와 8로 설정되었다. 최대 1GHz의 높은 입력신호를 처리하기 위해 cascade 구조의 preprocessing block을 적용하였으며, 전압 구동 방식 interpolation 기법을 적용하여 기준전압 생성 시 발생하는 추가적인 전력소모를 최소화하였다. 또한, 새로운 개념의 자체보정 벡터 발생기를 이용하여 device mismatch, 기생 저항 및 커패시턴스 등에 의한 offset error를 최소화하였다. 제안하는 ADC는 1.2V 0.13um 1-poly 7-metal CMOS 공정을 사용하여 설계 되었으며 calibration 회로를 포함한 유효 칩 면적은 2.5$mm^2$ 이다. 측정 결과 입력 주파수 9MHz, sampling 주파수 2GHz에서 39.49dB의 SNDR 특성을 보이며, calibration 회로의 작동결과 약 3dB 정도의 SNDR의 상승을 확인하였다.

• 한국전자통신학회논문지
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• 제16권3호
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• pp.417-422
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• 2021

본 논문에서는 시간영역 비교기를 응용한 ZQ 보정회로를 제안한다. 제안하는 비교기는 VCO기반으로 설계되었으며 전력소모를 감소시키기 위해 추가적인 클록 발생기를 사용하였다. 제안한 비교기를 사용하여 참조 전압과 PAD 전압을 낮은 1 LSB 전압 단위로 비교하여 추가적인 오프셋 보정과정을 생략할 수 있었다. 제안하는 시간영역 비교기 기반의 ZQ 보정회로는 1.05 V 및 0.5 V 공급전압의 65 nm CMOS공정으로 설계되었다. 제안한 클록 발생기를 통해 단일 시간영역 비교기 대비 37 %의 전력소모가 감소하였으며 제안하는 ZQ 보정 회로를 통해 최대 67.4 %의 mask margin을 증가시켰다.

• 전자공학회논문지
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• 제52권12호
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• pp.109-117
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• 2015

본 논문에서는 DSP(Digital Signal Processor)를 이용하여 LED(Light Emitting Diode)에 전류 또는 전압을 공급하고, 이에 따라 나타나는 전압 또는 전류 특성을 분석하는 시스템에서, 전원 공급 또는 측정하는 회로의 비선형 오차 및 임의로 발생하는 오차를 감소시키는 방법을 제안하였다. 임의 오차를 줄이기 위해서는 재귀 평균 방법을 이용하였으며, 비선형 오차를 줄이기 위해서는 보정과정에서 획득한 데이터들을 2차 다항 회귀분석 방법을 이용하여 보정계수를 구하였으며, 이를 이용하여 LED를 생산 시 측정하는 항목인 역방향전류(IR), 역방향 전압(VR), 순방향전압(VF1, VF2, VF3)에 적용하여 오차를 교정하였다. 실험 결과에서는 오차율이 0.017 ~ 0.043 %로 관찰되었다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.601-604
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• 2002

In this paper, the timing do-skew modeling for a high speed logic tester channels is developed. The time delay of each channel in a logic tester are different from other channels and it can produce timing error in a test. To get the best timing accuracy in the test with a logic tester, the timing skew must be compensated. The timing skew of channels is due to the difference of time delay of pin-electronics devices composing channels and length of metal line placed on PCB. The expected timing difference of channels can be calculated according to the specifications of pin electronics devices and strip line modeling of PCB. With the calculated delay time, the timing skew compensation circuit has been designed. With the timing skew compensation circuit, the timing calibration of a logic tester can be peformed easily and automatically without other time measuring instruments. The calibration method can then be directly applied to logic testers in mass production lines.