• 제목/요약/키워드: c-Si interface

검색결과 649건 처리시간 0.033초

PECVD와 NO 어닐링 공정을 이용하여 제작한 N-based 4H-SiC MOS Capacitor의 SiC/SiO2 계면 특성 (SiC/SiO2 Interface Characteristics in N-based 4H-SiC MOS Capacitor Fabricated with PECVD and NO Annealing Processes)

  • 송관훈;김광수
    • 전기전자학회논문지
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    • 제18권4호
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    • pp.447-455
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    • 2014
  • 본 연구에서는 4H-SiC MOSFET의 주요 문제점인 $SiC/SiO_2$ 계면의 특성을 향상시키기 위해 PECVD (plasma enhanced chemical vapor deposition) 공정을 이용하여 n-based 4H-SiC MOS Capacitor를 제작하였다. 건식 산화 공정의 낮은 성장속도, 높은 계면포획 밀도와 $SiO_2$의 낮은 항복전계 등의 문제를 극복하기 위하여 PECVD와 NO어닐링 공정을 사용하여 MOS Capacitor를 제작하였다. 제작이 끝난 후, MOS Capacitor의 계면특성을 hi-lo C-V 측정, I-V 측정 및 SIMS를 이용해 측정하고 평가하였다. 계면의 특성을 건식 산화의 경우와 비교한 결과 20% 감소한 평탄대 전압 변화, 25% 감소한 $SiO_2$ 유효 전하 밀도, 8MV/cm의 증가한 $SiO_2$ 항복전계 및 1.57eV의 유효 에너지 장벽 높이, 전도대 아래로 0.375~0.495eV만큼 떨어져 있는 에너지 영역에서 69.05% 감소한 계면 포획 농도를 확인함으로써 향상된 계면 및 산화막 특성을 얻을 수 있었다.

MTS를 사용한 LPCVD 법에 의한 (100)Si 위의 $\beta$-SiC 증착 및 계면특성 (Interfacial Characteristics of $\beta$-SiC Film Growth on (100) Si by LPCVD Using MTS)

  • 최두진;김준우
    • 한국세라믹학회지
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    • 제34권8호
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    • pp.825-833
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    • 1997
  • Silicon carbide films were deposited by low pressure chemical vapor deposition(LPCVD) using MTS(CH3SICl3) in hydrogen atmosphere on (100) Si substrate. To prevent the unstable interface from being formed on the substrate, the experiments were performed through three deposition processes which were the deposition on 1) as received Si, 2) low temperature grown SiC, and 3) carbonized Si by C2H2. The microstructure of the interface between Si substrates and SiC films was observed by SEM and the adhesion between Si substrates and SiC films was measured through scratch test. The SiC films deposited on the low temperature grown SiC thin films, showed the stable interfacial structures. The interface of the SiC films deposited on carbonized Si, however, was more stable and showed better adhesion than the others. In the case of the low temperature growth process, the optimum condition was 120$0^{\circ}C$ on carbonized Si by 3% C2H2, at 105$0^{\circ}C$, 5 torr, 10 min, showed the most stable interface. As a result of XRD analysis, it was observed that the preferred orientation of (200) plane was increased with Si carbonization. On the basis of the experimental results, the models of defect formation in the process of each deposition were compared.

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Sol-gel 법으로 합성된 SiC-C 복합분말을 사용하여 제조된 Si-SiC의 기계적 특성 및 전기저항 특성 (Mechanical and Electrical Properties of Si-SiC Fabricated Using SiC-C Composite Powders Synthesized by Sol-gel Process)

  • 윤성일;조경선;염미래;임대순;박상환
    • 한국세라믹학회지
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    • 제51권5호
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    • pp.459-465
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    • 2014
  • In this study, Si-SiC composites were fabricated using a Si melt infiltration method using ${\beta}$-SiC/C composite powders synthesized by the carbothermal reduction of $SiO_2-C$ precursors made from a TEOS and a phenol resin. The purity of the synthesized SiC-C composite powders was higher than 99.9993 wt% and the average particle size varied from 4 to $6{\mu}m$ with increasing carbon contents of the $SiO_2-C$ precursors. It was found that the Si-SiC composites fabricated in this study consist of ${\beta}$-SiC and residual Si, without any trace of ${\alpha}$-SiC. The 3-point bending strengths of the fabricated Si-SiC composites were measured and found to be higher than 550 MPa, although the density of the fabricated Si-SiC composite was less than $2.9g/cm^3$. The bending strengths and the densities of the fabricated Si-SiC composites were found to decrease with increasing C/Si mole ratios in the SiC-C composite powders. The specific resistivities of the Si-SiC composites fabricated using the SiC-C composite powders were less than $0.018{\Omega}cm$. With increasing C content in the SiC-C composite powders used for the fabrication of Si-SiC composites, the specific resistivity of the Si-SiC composites was found to slightly increase from 0.0157 to $0.018{\Omega}cm$.

Ag-Ti계 합금을 사용한 SiC/SiC 및 SiC/연강 브레이징에 대한 연구 (A Study on SiC/SiC and SiC/Mild steel brazing by the Ag-Ti based alloys)

  • 이형근;이재영
    • Journal of Welding and Joining
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    • 제14권4호
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    • pp.99-108
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    • 1996
  • The microstructure and bond strength are examined on the SiC/SiC and SiC/mild steel joints brazed by the Ag-Ti based alloys with different Ti contents. In the SiC/SiC brazed joints, the thickness of the reaction layers at the bond interface and the Ti particles in the brazing alloy matrices increase with Ti contents. When Ti is added up to 9 at% in the brazing alloy. $Ti_3SiC_2$ phase in addition to TiC and $Ti_5Si_3$ phase is newly created at the bond interface and TiAg phase is produced from peritectic reaction in the brazing alloy matrix. In the SiC/mild steel joints brazed with different Ti contents, the microstructure at the bond interface and in the brazing alloy matrix near SiC varies similarly to the case of SiC/SiC brazed joints. But, in the brazing alloy matrix near the mild steel, Fe-Ti intermetallic compounds are produced and increased with Ti contents. The bond strengths of the SiC/SiC and SiC/mild steel brazed joints are independent on Ti contents in the brazing alloy. There are no large differences of the bond strength between SiC/SiC and SiC/mild steel brazed joints. In the SiC/mild steel brazed joints, Fe dissolved from the mild steel does not affect on the bond strength of the joints. Thermal contraction of the mild steel has nearly no effects on the bond strength due to the wide brazing gap of specimens used in the four-point bend test. The brazed joints has the average bond strength of about 200 MPa independently on Ti contents, Fe dissolution and joint type. Fracture in four-point bend test initiates at the interface between SiC and TiC reaction layer and propagates through SiC bulk. The adhesive strength between SiC and TiC reaction layer seems to mainly control the bond strength of the brazed joints.

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4H-SiC DMOSFETs의 계면 전하 밀도에 따른 스위칭 특성 분석 (Effect of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs)

  • 강민석;문경숙;구상모
    • 한국전기전자재료학회논문지
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    • 제23권6호
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    • pp.436-439
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    • 2010
  • SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states ($Q_f$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the $SiO_2$/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of $SiO_2$/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.

SiCf/SiC 복합체의 특성에 미치는 열간가압소결 조건의 영향 (Effects of Hot Pressing Condition on the Properties of SiCf/SiC Composites)

  • 노비얀토 알피안;윤당혁
    • 한국세라믹학회지
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    • 제48권5호
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    • pp.335-341
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    • 2011
  • Continuous SiC fiber-reinforced SiC-matrix composites ($SiC_f$/SiC) had been fabricated by electrophoretic infiltration combined with ultrasonication. Nano-sized ${\beta}$-SiC added with 12 wt% of $Al_2O_3-Y_2O_3$ additive and Tyranno$^{TM}$-SA3 fabric were used as a matrix phase and fiber reinforcement, respectively. After hot pressing at 5 different conditions, the density, microstructure and mechanical properties of $SiC_f$/SiC were characterized. Hot pressing at relatively severe conditions, such as $1750^{\circ}C$ for 1 and 2 h, resulted in a brittle fracture behavior due to the strong fiber-matrix interface in spite of their high flexural strength. On the other hand, toughened $SiC_f$/SiC composite could be achieved by hot pressing at milder condition because of the formation of weak interface in spite of the decreased flexural strength. These results proposed the importance of weak fiber-matrix interface in the fabrication of ductile $SiC_f$/SiC composite.

Impact of Interface Charges on the Transient Characteristics of 4H-SiC DMOSFETs

  • Kang, Min-Seok;Bahng, Wook;Kim, Nam-Kyun;Ha, Jae-Geun;Koh, Jung-Hyuk;Koo, Sang-Mo
    • Journal of Electrical Engineering and Technology
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    • 제7권2호
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    • pp.236-239
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    • 2012
  • In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

비정질 실리콘 태양전지의 p-a-SiC:H/i-a-Si:H 계면에 삽입된 P형 미세 결정 실리콘의 완충층 효과에 대한 수치 해석 (Numerical Simulation on Buffering Effects of Ultrathin p-${\mu}c$-Si:H Inserted at the p-a-SiC:H/i-a-Si:H Interface of Amorphous Silicon Solar Cells)

  • 이창현;임굉수
    • 태양에너지
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    • 제20권1호
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    • pp.11-20
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    • 2000
  • To get more insight into the buffering effects of the p-${\mu}c$-Si:H Inserted at the p-a-SiC:H/i-a-Si:H interface, we present a systematic numerical simulation using Gummel-Schafetter method. The reduced recombination loss at the p/i interface due to a constant bandgap buffer is analysed in terms of the variation of the p/i Interface region with a short lifetime and the characterisitics of the buffer such as mobility bandgap, acceptor concentration, and D-state density. The numerical modeling on the constant bandgap buffer demonstrates clearly that the buffering effects of the thin p-${\mu}c$-Si:H originate from the shrinkage of highly defective region with a short lifetime in the vicinity of the p/i interface.

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SiC/$SiO_2$ 계면의 고온 기공발생에 관한 열역학적 계산 (Thermodynamic Calculations of High Temperature Bubble Formation at SiC/$SiO_2$ Interface)

  • 이문희;박종욱
    • 한국세라믹학회지
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    • 제27권4호
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    • pp.543-547
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    • 1990
  • Numerous researchers have observed the bubble fromation at SiC/SiO2 interface from 130$0^{\circ}C$ to 1$700^{\circ}C$. According to thermodynamic calculation, the bubble could be formed from the microscopic impurities which result from the chemical vapor deposition of SiC. When C-impurity is present at the interface, it is calculated that the bubble is formed at 1511$^{\circ}C$ and when Si is present, the bubble is formed at 177$0^{\circ}C$. These results are very close to the prior observations, but the calculation can not explain the observation of bubble below 150$0^{\circ}C$.

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4H-SiC와 산화막 계면에 대한 혼합된 일산화질소 가스를 이용한 산화 후속 열처리 효과 (Effect of High-Temperature Post-Oxidation Annealing in Diluted Nitric Oxide Gas on the SiO2/4H-SiC Interface)

  • 김인규;문정현
    • 한국전기전자재료학회논문지
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    • 제37권1호
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    • pp.101-105
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    • 2024
  • 4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (Ron,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (Dit) at the SiO2/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO2/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N2 diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N2 gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO2/4H-SiC interface, thereby reducing the Dit.