• Journal of IKEEE
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• v.18 no.4
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• pp.447-455
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• 2014

In this research, n-based 4H-MOS Capacitor was fabricated with PECVD (plasma enhanced chemical vapor deposition) process for improving SiC/$SiO_2$ interface properties known as main problem of 4H-SiC MOSFET. To overcome the problems of dry oxidation process such as lower growth rate, high interface trap density and low critical electric field of $SiO_2$, PECVD and NO annealing processes are used to MOS Capacitor fabrication. After fabrication, MOS Capacitor's interface properties were measured and evaluated by hi-lo C-V measure, I-V measure and SIMS. As a result of comparing the interface properties with the dry oxidation case, improved interface and oxide properties such as 20% reduced flatband voltage shift, 25% reduced effective oxide charge density, increased oxide breakdown field of 8MV/cm and best effective barrier height of 1.57eV, 69.05% reduced interface trap density in the range of 0.375~0.495eV under the conduction band are observed.

• Journal of the Korean Ceramic Society
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• v.34 no.8
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• pp.825-833
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• 1997

Silicon carbide films were deposited by low pressure chemical vapor deposition(LPCVD) using MTS(CH3SICl3) in hydrogen atmosphere on (100) Si substrate. To prevent the unstable interface from being formed on the substrate, the experiments were performed through three deposition processes which were the deposition on 1) as received Si, 2) low temperature grown SiC, and 3) carbonized Si by C2H2. The microstructure of the interface between Si substrates and SiC films was observed by SEM and the adhesion between Si substrates and SiC films was measured through scratch test. The SiC films deposited on the low temperature grown SiC thin films, showed the stable interfacial structures. The interface of the SiC films deposited on carbonized Si, however, was more stable and showed better adhesion than the others. In the case of the low temperature growth process, the optimum condition was 120$0^{\circ}C$ on carbonized Si by 3% C2H2, at 105$0^{\circ}C$, 5 torr, 10 min, showed the most stable interface. As a result of XRD analysis, it was observed that the preferred orientation of (200) plane was increased with Si carbonization. On the basis of the experimental results, the models of defect formation in the process of each deposition were compared.

• Journal of the Korean Ceramic Society
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• v.51 no.5
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• pp.459-465
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• 2014

In this study, Si-SiC composites were fabricated using a Si melt infiltration method using ${\beta}$-SiC/C composite powders synthesized by the carbothermal reduction of $SiO_2-C$ precursors made from a TEOS and a phenol resin. The purity of the synthesized SiC-C composite powders was higher than 99.9993 wt% and the average particle size varied from 4 to $6{\mu}m$ with increasing carbon contents of the $SiO_2-C$ precursors. It was found that the Si-SiC composites fabricated in this study consist of ${\beta}$-SiC and residual Si, without any trace of ${\alpha}$-SiC. The 3-point bending strengths of the fabricated Si-SiC composites were measured and found to be higher than 550 MPa, although the density of the fabricated Si-SiC composite was less than $2.9g/cm^3$. The bending strengths and the densities of the fabricated Si-SiC composites were found to decrease with increasing C/Si mole ratios in the SiC-C composite powders. The specific resistivities of the Si-SiC composites fabricated using the SiC-C composite powders were less than $0.018{\Omega}cm$. With increasing C content in the SiC-C composite powders used for the fabrication of Si-SiC composites, the specific resistivity of the Si-SiC composites was found to slightly increase from 0.0157 to $0.018{\Omega}cm$.

• Journal of Welding and Joining
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• v.14 no.4
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• pp.99-108
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• 1996

The microstructure and bond strength are examined on the SiC/SiC and SiC/mild steel joints brazed by the Ag-Ti based alloys with different Ti contents. In the SiC/SiC brazed joints, the thickness of the reaction layers at the bond interface and the Ti particles in the brazing alloy matrices increase with Ti contents. When Ti is added up to 9 at% in the brazing alloy. $Ti_3SiC_2$ phase in addition to TiC and $Ti_5Si_3$ phase is newly created at the bond interface and TiAg phase is produced from peritectic reaction in the brazing alloy matrix. In the SiC/mild steel joints brazed with different Ti contents, the microstructure at the bond interface and in the brazing alloy matrix near SiC varies similarly to the case of SiC/SiC brazed joints. But, in the brazing alloy matrix near the mild steel, Fe-Ti intermetallic compounds are produced and increased with Ti contents. The bond strengths of the SiC/SiC and SiC/mild steel brazed joints are independent on Ti contents in the brazing alloy. There are no large differences of the bond strength between SiC/SiC and SiC/mild steel brazed joints. In the SiC/mild steel brazed joints, Fe dissolved from the mild steel does not affect on the bond strength of the joints. Thermal contraction of the mild steel has nearly no effects on the bond strength due to the wide brazing gap of specimens used in the four-point bend test. The brazed joints has the average bond strength of about 200 MPa independently on Ti contents, Fe dissolution and joint type. Fracture in four-point bend test initiates at the interface between SiC and TiC reaction layer and propagates through SiC bulk. The adhesive strength between SiC and TiC reaction layer seems to mainly control the bond strength of the brazed joints.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.6
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• pp.436-439
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• 2010

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. In this work, we report the effect of the interface states ($Q_f$) on the transient characteristics of SiC DMOSFETs. The key design parameters for SiC DMOSFETs have been optimized by using a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. When the $SiO_2$/SiC interface charge decreases, power losses and switching time also decrease, primarily due to the lowered channel mobilities. High density interface states can result in increased carrier trapping, or more recombination centers or scattering sites. Therefore, the quality of $SiO_2$/SiC interfaces has a important effect on both the static and transient properties of SiC MOSFET devices.

• Journal of the Korean Ceramic Society
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• v.48 no.5
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• pp.335-341
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• 2011

Continuous SiC fiber-reinforced SiC-matrix composites ($SiC_f$/SiC) had been fabricated by electrophoretic infiltration combined with ultrasonication. Nano-sized ${\beta}$-SiC added with 12 wt% of $Al_2O_3-Y_2O_3$ additive and Tyranno$^{TM}$-SA3 fabric were used as a matrix phase and fiber reinforcement, respectively. After hot pressing at 5 different conditions, the density, microstructure and mechanical properties of $SiC_f$/SiC were characterized. Hot pressing at relatively severe conditions, such as $1750^{\circ}C$ for 1 and 2 h, resulted in a brittle fracture behavior due to the strong fiber-matrix interface in spite of their high flexural strength. On the other hand, toughened $SiC_f$/SiC composite could be achieved by hot pressing at milder condition because of the formation of weak interface in spite of the decreased flexural strength. These results proposed the importance of weak fiber-matrix interface in the fabrication of ductile $SiC_f$/SiC composite.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• Solar Energy
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• v.20 no.1
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• pp.11-20
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• 2000

To get more insight into the buffering effects of the p-${\mu}c$-Si:H Inserted at the p-a-SiC:H/i-a-Si:H interface, we present a systematic numerical simulation using Gummel-Schafetter method. The reduced recombination loss at the p/i interface due to a constant bandgap buffer is analysed in terms of the variation of the p/i Interface region with a short lifetime and the characterisitics of the buffer such as mobility bandgap, acceptor concentration, and D-state density. The numerical modeling on the constant bandgap buffer demonstrates clearly that the buffering effects of the thin p-${\mu}c$-Si:H originate from the shrinkage of highly defective region with a short lifetime in the vicinity of the p/i interface.

• Journal of the Korean Ceramic Society
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• v.27 no.4
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• pp.543-547
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• 1990

Numerous researchers have observed the bubble fromation at SiC/SiO2 interface from 130$0^{\circ}C$ to 1$700^{\circ}C$. According to thermodynamic calculation, the bubble could be formed from the microscopic impurities which result from the chemical vapor deposition of SiC. When C-impurity is present at the interface, it is calculated that the bubble is formed at 1511$^{\circ}C$ and when Si is present, the bubble is formed at 177$0^{\circ}C$. These results are very close to the prior observations, but the calculation can not explain the observation of bubble below 150$0^{\circ}C$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.101-105
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• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.