• 제목/요약/키워드: bus interface

검색결과 246건 처리시간 0.027초

Research on the Continuous Use Intention of Mobile Bus Payment App from the Perspective of user Quality Perception

  • Li, Shuo;Sun, Cong-Ying
    • 한국컴퓨터정보학회논문지
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    • 제27권9호
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    • pp.217-224
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    • 2022
  • 본 연구는 D&M 모델과 ECM모델을 기반으로 소비자가 대중교통 모바일 결제 앱을 지속적으로 사용하는 데 영향을 미치는 연구 모델을 구축하였다. 온라인 설문조사를 통해 중국 베이징지역에서 264개의 유효한 설문지를 획득하여 Smartpls3.0으로 분석하였다. 연구 결과는, 지각된 정보의 질, 지각된 시스템의 질, 그리고 지각된 인터페이스 설계의 질은 지각된 유용성과 만족을 통하여 소비자 지속적 사용의도에 유의한 긍정적 영향을 미치는 것으로 나타났다. 지각된 기능의 질은 단지 지각된 유용성만을 통해 지속적 사용의도에 긍정적인 영향을 미치는 것이다.

3.3V, 400MBPS IEEE-1394 물리층 트랜시버의 설계 (Design of A 3.3V, 400 MBPS IEEE-1394 Physical Layer Transceiver)

  • 황인철;한상찬송병준김수원
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.783-786
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    • 1998
  • We designed a 3.3 V, 400 Mbps IEEE-1394 physical layer transeiver on 0.6um 1P3M CMOS process. The transceiver drives a twisted pair cable of which differential impedance is 110 $\Omega$ so that differential amplitude reaches 200 mV at 400 Mbps and restores this small signal to rail-to-rail. Also, the transceiver arbitrates the interface among nodes on a bus configuration and supports both synchronous interface and asynchronous interface.

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통신방송위성 탑재체 정합시험 방법에 관한연구 (Interface Test Method for Communications and Broadcasting Satellite Payload)

  • 김신홍;김인준;최완식;이성팔
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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    • pp.291-294
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    • 2002
  • This paper proposed interface test method for performance verification of communication and broadcasting satellite between communication and broadcasting satellite payload and EGSE(Electrical Ground Support Equipment). We need ground support equipment for test them to performance verification and conform interface function of payload. This paper define tile telemetry transfer method for control payload using GSE(Ground Support Equipment) and receive telemetry data collected from GSE through bus simulator

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SOC Bus Transaction Verification Using AMBA Protocol Checker

  • Lee, Kab-Joo;Kim, Si-Hyun;Hwang, Hyo-Seon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제2권2호
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    • pp.132-140
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    • 2002
  • This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

디지탈 신호처리소자 TMS320C30을 이용한 고속 영상처리 프로세서의 개발 (Development of a High-speed Image Processing Processor using TMS320C30 DSP)

  • 변중남;오상록;유범재;한동일;김재옥
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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    • pp.439-442
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    • 1990
  • A powerful general purpose image processing processor is developed using a high-speed DSP chip, TMS320C30. The image processing processor, compatible to the standard VME bus, is composed of VME bus interface unit, video rate image grabbing/coding unit, TMS320C30 interface unit and bank of high-speed SRAMs. The performance is evaluated experimentally with the general image processing algorithms and the results show that the developed processor is capable of high speed image processing.

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Graphic User Interface Scheme for Wireless Universal Serial Bus

  • Lee, Hyun-Jeong;Kim, Jong-Won;Huh, Jae-Doo
    • 한국정보기술응용학회:학술대회논문집
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    • 한국정보기술응용학회 2005년도 6th 2005 International Conference on Computers, Communications and System
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    • pp.183-186
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    • 2005
  • WUSB is a new technology which combines the speed and the security of wired USB with the easy use of wireless technology. In this paper, GUI for WUSB is designed and implemented to show the connectivity and contents of the WUSB devices. Also, the proposed GUI shows the log window while content transfers occur between the host and device. The proposed GUI can be used for various wireless technologies which provide wireless function with existing USB hosts and devices.

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토큰 패싱 버스 네트워크에서의 망 접속기 구현에 관한 연구 (Implementation of Network Interface Unit for Token Passing Bus Network)

  • 추영열;정범진;김덕우;임용제
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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    • pp.926-929
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    • 1988
  • In this paper, the implementation of NIU (Network Interface Unit) for Token Passing Bus network is studied. The network is based on the IEEE 802.4 standard, which is the basis of MAP. IBM-PC is chosen as host station. The structure of the network and NIU is investigated and the implementation is illustrated. The logical ring constructed following the standard. Transmission and reception of data are tested. The experimental results are referred.

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다중프로세서시스테멩 대한 파이프라인 방식 메모리 접근제어의 설계와 그 효율분석 (A Design of Pipelined Memory Access Control for Multiprocessor Systems and its Evaluation)

  • 김정두;손윤구
    • 대한전자공학회논문지
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    • 제25권8호
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    • pp.927-936
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    • 1988
  • This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

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Preliminary Design of Electronic System for the Optical Payload

  • Kong Jong-Pil;Heo Haeng-Pal;Kim YoungSun;Park Jong-Euk;Chang Young-Jun
    • 대한원격탐사학회:학술대회논문집
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    • 대한원격탐사학회 2005년도 Proceedings of ISRS 2005
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    • pp.637-640
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    • 2005
  • In the development of a electronic system for a optical payload comprising mainly EOS(Electro-Optical Sub-system) and PDTS(Payload Data Transmission Sub-system), many aspects should be investigated and discussed for the easy implementation, for th e higher reliability of operation and for the effective ness in cost, size and weight as well as for the secure interface with components of a satellite bus, etc. As important aspects the interfaces between a satellite bus and a payload, and some design features of the CEU(Camera Electronics Unit) inside the payload are described in this paper. Interfaces between a satellite bus and a payload depend considerably on whether t he payload carries the PMU(Payload Management Un it), which functions as main controller of the Payload, or not. With the PMU inside the payload, EOS and PDTS control is performed through the PMU keep ing the least interfaces of control signals and primary power lines, while the EOS and PDTS control is performed directly by the satellite bus components using relatively many control signals when no PMU exists inside the payload. For the CEU design the output channel configurations of panchromatic and multi-spectral bands including the video image data inter face between EOS and PDTS are described conceptually. The timing information control which is also important and necessary to interpret the received image data is described.

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다자간 화상회의 시스템에서의 동시 전송방법에 의한 데이터 입출력 시간 단축 방안 (Data Input/Output Time Reduction Scheme with the Simultaneous Transmission Method for Multi-participants Video Conference System)

  • 김현기
    • 한국멀티미디어학회논문지
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    • 제3권3호
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    • pp.234-240
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    • 2000
  • 본 논문에서는 멀티미디어 데이터 스트림이 기존의 시스템 버스를 이용하여 네트워크 접속장치로부터 주기억 장치 및 멀티미디어 처리장치에 동일한 데이터가 동시에 전송될 수 있는 방법을 제 안한다. 제안한 방법은 시스템 버스 내부의 데이터 흐름을 개선하고, 멀티미디어 데이터의 입출력 시간을 단축시킬 수 있다. 또한, 본 논문에서 제안한 방법을 다자간 화상회의 시스템에 적용하여 참석자 수에 따른 시스템 버스의 사용횟수, 버스사이클 및 데이터의 전송시간을 기존의 방법과 비교하였다. 성능비교 결과, 제안한 방법이 기존의 방법보다 참석자의 수에 관계없이 시스템 버스의 사용횟수는 50%, 전송시간은 75%씩 감소되리라 예상된다.

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