• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.28B no.5
• /
• pp.404-410
• /
• 1991

In this paper,a network interface unit of token-passing bus network and its driving software are implemented based on Mini-MAP. This network interface unit performs the function of MAC layer which is responsible for transmission and reception of frames as well as the management of logical ring. The driving software performs the management of data buffer and the report of errors, if ocoured, to the higher layer. Motorola MC68824 of is used as a TBC(Token Bus Controller) and Intel80186 as a CPU for network interface unit. The operation of network interface unit is verified by self-test which checks the functioning of TBC and CPU. In addition each module of driving software is tested to check the functions regarding transmission and reception of frames.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.32B no.8
• /
• pp.1064-1073
• /
• 1995

On a bus-based shared memory multiprocessing system, the system bus monitoring and analysis are crucial for system integration test and performance analysis. In this paper, the design and implementation of a bus monitoring instrument for the TICOM-III system are decribed. The instrument dedicated to TICOM-III, which is called the Bus Information Procssing Unit, analyzes the bus state and measures the bus utilization. It performs many useful functions to help debugging the system, and offers a simple user interface.

• Proceedings of the Korea Contents Association Conference
• /
• 2004.11a
• /
• pp.327-332
• /
• 2004

USB(Universal Serial Bus) is one of the most popular communication interfaces. When USB is used in an extended range, especially configurating In-home network by connecting multiple digital devices each other, USB interface uses the bandwidth in the way of TDM(Time Division Multiplexing) so that the bottleneck of bus bandwidth can be brought. In this paper, the more effective usage of bus bandwidth to overcome this situation is introduced. Basically, in order to realize the system for transferring realtime moving picture data among digital information devices, we analyze USB transfer types and Descriptors and introduce the method to upgrade detailed performance of Isochronous transfer that is one of USB transfer types. In the case that Configuration descriptor of a device has Interface descriptor that has two AlternateSetting, if Isochronous transfers are not processed smoothly due to excessive bus traffic, the application of the device changes AlternateSetting of the Interface descriptor and requires a new configuration by SetInterface() request. As a result of this adaptive configuration, the least data frame rate is guaranteed to a device that the sufficient bandwidth is not alloted. And if the bus traffic is normal, the algorithm to return to the original AlteranteSetting is introduced. this introduced method resolve the bottleneck of moving picture transfer that can occur in home network connected by multiple digital devices.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.1037-1040
• /
• 1999

In this paper, we designed the extended ATA(AT Attachment interface with extension) interface that combines with goods price and ability and intellectual behavior of SCSI, for make progress the ability and structure of ordinary interface for connect with device of using PC. ATA is establish a standard of IDE(Intelligent Drive Electronics) public in small form factor. SCSI bus is device behaving intellectual and have stable hardware structure, calssified instructions structure. But it is device that difficult to buy, because of price of more than two times. The other side, ATA device is worse than SCSI bus in part of ability, but it came to SCSI in part of speed after improve and it's price is less expensive. another improvement of ATA is a standard of ARAP(AT Attachment Packet Interface) and use method of packet transmission and behaves as if SCSI use a method. Finally, improvement of ATAPI behave from interface of only HDD to ability of ordinary interface. This paper propose the structure of extended interface that satisfied the price and ability.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.7
• /
• pp.10-16
• /
• 1999

This paper describes a low voltage swing bus driver using FCSR(Feedback Control Swing voltage Reduction) which can control bus swing voltage within a few hundred of mV. It is proposed to reduce power consumption in On-chip interface, especially for MDL(Merged DRAM Logic) architecture wihich has wide and large capacitance bus. FCSR operates on differential signal dual-line bus and on precharged bus with block controlling fuction. We modeled driver and bus to scale driver size automatically when bus environment is variant. We also modeled coupling capacitance noise(crosstalk) of neighborhood lines which operate on odd mode with parallel current source to analysis crosstalk effect in the victim-line according as voltage transition in the aggressor-line and environment in the victim-line. We built a test chip which was designed to swing 600mV in bus, shows 70Mhz operation at 3.3V, using Hyundai 0.8um CMOS technology. FCSR operate with 250Mhz at 3.3V by Hspice simulation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.539-542
• /
• 2002

본 논문에서 는 64채널 DWDM(Dense Wavelength Division Multiplexing)용 광원(Optical Source)을 구현하고, 이를 효율적으로 제어하기 위하여 I$^2$C Bus interface를 이용한 제어기를 설계하였다. 채널은 독립적으로 동작될 수 있도록 각각 Laser Diode 구동 회로와 마이크로프로세서, A/D 및 D/A 컨버터로 구성하였으며, 또한 각 채널들은 하나의 I$^2$C Bus를 통해 주 제어기와 연결된다 주 제어기는 RS-232 및 LAN을 통해 틀어오는 사용자의 명령을 I$^2$C Bus를 이용하여 각 채널에 전달하고, 채널로부터 들어오는 정보를 사용자에게 제공한다. RS-232C 및 LAN을 통한 PC와의 전송속도는 57600BPS로 구현하였다.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3067-3069
• /
• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.11 no.2
• /
• pp.89-94
• /
• 2011

Today, the utilization of communication devices is being increased including information terminals, cell phones, handheld personal digital assistants (PDA) caused by the development of information and communication technology. The development of information and services is speeding up, whereas most communication devices have provided a inefficient hierarchical menu and sequential searching structure. In this study, the Adaptive User Interface is applied to the Bus Information Terminal(BIT) which is one of communication equipment installed in the bus stop. It will be based on analysis of unspecified individuals' preferences and user's directly personalization in the BIT prototype. We expect the results of this study to be possible to provide users with efficient and convenient information acquisition and contribute to the development of public transport use by improving the accessibility and usability of BIT.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.2
• /
• pp.437-444
• /
• 2010

The audio data have been communicated using analog methods or simple protocols. However, with the advent and improvement of various multimedia functions, many audio devices have been integrated into a mobile handset in which interconnection lines are very complicated. Conventional point-to-point connections such as $I^2S$ and PCM demand more power consumption whenever more devices are attached. In this paper, we design a common bus digital audio interface that communicates with only two wires and employs the clock gear method to reduce bus power consumption. The comparison results show that the proposed common bus connection can reduce more than 30% of power consumption as compared with point-to-point connection if more than three devices are connected.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.3
• /
• pp.684-690
• /
• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.