• Title/Summary/Keyword: bumps

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Electromigration Behavior of the Flip-Chip Bonded Sn-3.5Ag-0.5Cu Solder Bumps (플립칩 본딩된 Sn-3.5Ag-0.5Cu 솔더범프의 electromigration 거동)

  • Choi Jae-Hoon;Jun Sung-Woo;Won Hae-Jin;Jung Boo-Yang;Oh Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.11 no.4 s.33
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    • pp.43-48
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    • 2004
  • Electromigration of Sn-3.5Ag-0.5Cu solder bumps was investigated with current densities of $3{\~}4{\times}10^4 A/cm^2$ at temperatures of $130{\~}160^{\circ}C$ using flip chip specimens which consisted of upper Si chip and lower Si substrate. Electromigration failure of the Sn-3.5Ag-0.5Cu solder bump occurred with complete consumption of Cu UBM and void formation at cathode side of the solder bump. The activation energies for electromigration of the Sn-3.5Ag-0.5Cu solder bump were measured as 0.61 eV at current density of $3{\times}10^4 A/cm^2$, 0.63 eV at $3.5{\times}10^4 A/cm^2$, and 0.77 eV at $4{\times}10^4 A/cm^2$, respectively.

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Thermal Cycling and High Temperature Storage Reliabilities of the Flip Chip Joints Processed Using Cu Pillar Bumps (Cu Pillar 플립칩 접속부의 열 싸이클링 및 고온유지 신뢰성)

  • Kim, M.Y.;Lim, S.K.;Oh, T.S.
    • Journal of the Microelectronics and Packaging Society
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    • v.17 no.3
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    • pp.27-32
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    • 2010
  • For the flip chip joints processed using Cu pillar bumps and Sn pads, thermal cycling and high temperature storage reliabilities were examined as a function of the Sn pad height. With increasing the height of the Sn pad, which composed of the flip chip joint, from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance of the flip chip joint decreased from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$. Even after thermal cycles of 1000 times ranging from $-45^{\circ}C$ to $125^{\circ}C$, the Cu pillar flip chip joints exhibited the contact resistance increment below 12% and the shear failure forces similar to those before the thermal cycling test. The contact resistance increment of the Cu pillar flip chip joints was maintained below 20% after 1000 hours storage at $125^{\circ}C$.

Surface Roughness of the Electroplated Sn with Variations of Electrodeposition Parameters and Contact Resistance of the Flip-chip-bonded Sn Bumps (Electrodeposition 변수에 따른 Sn 도금의 표면 거칠기와 플립칩 접속된 Sn 범프의 접속저항)

  • Jung, Boo-Yang;Park, Sun-Hee;Kim, Young-Ho;Oh, Tae-Sung
    • Journal of the Microelectronics and Packaging Society
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    • v.13 no.4
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    • pp.37-43
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    • 2006
  • Surface roughness and hardness of the electroplated Sn were characterized with variations of electroplating current density and current mode. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the surface roughness of $2.0{\sim}2.4{\mu}m$. The Sn electroplated with pulse current mode exhibited low surface roughness compared one processed with direct current mode. With surface annealing at $300^{\circ}C$ for 3 sec using halogen lamp, surface roughness of the Sn bump was substantially reduced to $1{\mu}m$. The Sn electroplated at $5{\sim}50mA/cm^{2}$ exhibited the hardness of 10 Hv. Low contact resistances of $33{\sim}17m{\Omega}$ were obtained for specimens flip-chip bonded with Sn bumps.

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Fabrication and Characteristics of Electroless Ni Bump for Flip Chip Interconnection (Flip Chip 접속을 위한 무전해 니켈 범프의 형성 및 특성 연구)

  • Jeon, Yeong-Du;Im, Yeong-Jin;Baek, Gyeong-Ok
    • Korean Journal of Materials Research
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    • v.9 no.11
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    • pp.1095-1101
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    • 1999
  • Electroless Ni plating is applied to form bumps and UBM layer for flip chip interconnection. Characteristics of electroless Ni are also investigated. Zincate pretreatment is analyzed and plated layer characteristics are investigated according to variables like temperature, pH and heat treatment. Based on these observations, characteristics dependence to each variables and optimum electroless Ni plating conditions for flip-chip interconnection are suggested. Electroless Ni has 10wt% P, $60\mu\Omega$-cm resistivity, 500HV hardness and amorphous structure. It changes crystallized structure and hardness increases after heat treatment After interconnection of electroless Ni bumps by ACF flip chip method, we show their advantages and possibility in microelectronic package applications.

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Characteristics of Plated Bump on Multi-layer Build up PCB by Pulse-reverse Electroplating (Pulse-reverse도금을 이용한 다층 PCB 빌드업 기판용 범프 생성특성)

  • Seo, Min-Hye;Kong, Man-Sik;Hong, Hyun-Seon;Sun, Jee-Wan;Kong, Ki-Oh;Kang, Kae-Myung
    • Korean Journal of Materials Research
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    • v.19 no.3
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    • pp.151-155
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    • 2009
  • Micro-scale copper bumps for build-up PCB were electroplated using a pulse-reverse method. The effects of the current density, pulse-reverse ratio and brightener concentration of the electroplating process were investigated and optimized for suitable performance. The electroplated micro-bumps were characterized using various analytical tools, including an optical microscope, a scanning electron microscope and an atomic force microscope. Surface analysis results showed that the electroplating uniformity was viable in a current density range of 1.4-3.0 A/$dm^2$ at a pulse-reverse ratio of 1. To investigate the brightener concentration on the electroplating properties, the current density value was fixed at 3.0 A/$dm^2$ as a dense microstructure was achieved at this current density. The brightener concentration was varied from 0.05 to 0.3 ml/L to study the effect of the concentration. The optimum concentration for micro-bump electroplating was found to be 0.05 ml/L based on the examination of the electroplating properties of the bump shape, roughness and grain size.

OPERATIONAL MODEL OF TIME-KEEPING SYSTEMS OF HEUMGYEONGGAK-NU (흠경각루 시보시스템의 작동모델)

  • KIM, SANG HYUK;YUN, YONG-HYUN;MIHN, BYEONG-HEE;LEEM, BYONG GUEN;YOON, MYUNG KYOON;LEEM, BYONG SI
    • Publications of The Korean Astronomical Society
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    • v.34 no.3
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    • pp.31-40
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    • 2019
  • We study the internal structure under the artificial mountain of Heumkyeonggak-nu, a Korean water-powered clock in the early Joseon dynasty. All the puppets on the artificial mountain are driven by the rotational force generated by the water wheel at their designated time. We design a model that work with three parts of the artificial mountain. At the upper part of the artificial mountain to the east, west, north and south, there are four puppets called the Four Mystical Animal Divinity and four ladies called the Jade Lady respectively. The former rotates a quarter every double hour and the latter rings the bell every hour. In the middle part of this mountain is the timekeeping platform with four puppets; the Timekeeping Official (Hour Jack), the Bell-, Drum-, and Gong-Warriors. The Hour Jack controls time with three warriors each hitting his own bell, drum, and gong, respectively. In the plain there are 12 Jade Lady puppets (the lower ladies) combined with 12 Oriental Animal Deity puppets. In his own time a lady doll pops out of the hole and her animal doll gets up. Two hours later, the animal deity lies down and his lady hides in the artificial plain. These puppets are regularly moved by the signal such as iron balls, bumps, levers, and so on. We can use balls and bumps to explain the concept of the Jujeon system. Iron balls were used to manipulate puppets of the timekeeping mechanism in Borugak-nu, another Korean water-powered clock in Joseon dynasty, which was developed earlier than Heumgyeonggak-nu. According to the North Korea's previous study (Choi, 1974), it is obvious that bumps were used in the internal structure of Heumgyeonggak-nu. In 1669, The armillary clock made by Song, I-young was also utilized bumps. Finally we presented mock-ups of three timekeeping systems.

Study on wear characteristics of commercialized HDD slider pad (상용 하드디스크 슬라이더 패드의 마모 특성에 관한 연구)

  • Jang, Cheol-Eun;Kim, Dae-Eun
    • Transactions of the Society of Information Storage Systems
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    • v.3 no.3
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    • pp.139-143
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    • 2007
  • In recent years new recording media and materials for head-disk interface (HDI) have been developed in order to increase the recording density of storage devices and decrease the cost of production. It is well known that HDI in hard disk drive (HDD) needs high durability and stability. The tribological characteristic of commercialized HDI systems is an important indicator of the HDD reliability. In this study, experimental investigation on the wear coefficient of commercialized hard disk slider pads was performed. The slider was placed on top of a hard disk and allowed to slide for a set distance. The wear of the pads was measured after the sliding tests. The result showed that the micro-bumps in commercialized HDD have extremely low wear coefficient of $10^{-11}$. The results of this work may be used for further development of the HDI technology for HDD.

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COG(chip on glass) 구조에서 유리를 투과하는 레이저 조사 방식에 의한 area array type 패키지의 마운팅 공정

  • 이종현;김원용;이용호;김영석
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2001.07a
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    • pp.119-126
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    • 2001
  • Chip-on-glass(COG) mounting of area array electronic packages was attempted by heating the rear surface of a contact pad film deposited on a glass substrate. The pads consisted of an adhesion(i.e. Cr or Ti) and a top coating layer(i.e. Ni or Cu) was heated by an UV laser beam transmitted through the glass substrate. The laser energy absorbed on the pad raised the temperature of a solder ball which is in physical contact with the pad, forming a reflowed solder bump. The effects of the adhesion and top coating layer on the laser reflow soldering were studied by measuring temperature profile of the ball during the laser heating process. The results were discussed based on the measurement of reflectivity of the adhesion layer. In addition, the microstructures of solder bumps and their mechanical properties were examined.

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Self-Assembling Adhesive Bonding by Using Fusible Alloy Paste for Microelectronics Packaging

  • Yasuda, Kiyokazu
    • Journal of the Microelectronics and Packaging Society
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    • v.18 no.3
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    • pp.53-57
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    • 2011
  • In the modern packaging technologies highly condensed metal interconnects are typically formed by highcost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, the unique concept and methodology of self-assembly even in micro-meter scale were developed. In this report we focus on the factors which influenced the self-formed bumps by analyzing the phenomenon experimentally. In case of RMA flux, homogenous pattern was obtained in both plain surface and cross-section surface observation. By using RA flux, the phenomena were accelerated although the self-formtion results was inhomogenous. With ussage of moderate RA flux, reaction rate of the self-formation was accelerated with homogeneous pattern.

The Stability of Plating Solution and the Current Density Characteristics of the Sn-Ag Plating for the Wafer Bumping

  • Kim, Dong-Hyun;Lee, Seong-Jun
    • Journal of the Korean institute of surface engineering
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    • v.50 no.3
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    • pp.155-163
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    • 2017
  • In this study, the effects of the concentration of metal ions and the applied current density in the Sn-Ag plating solutions were examined in regards to the resulting composition and morphology of the solder bumps' surface. Furthermore the effect of any impurities present in the methanesulfonic acid used as a base acid in the Sn-Ag solder plating solution on the stability of plating solution as well as the characteristics of the Sn-Ag alloys films was also explored. As expected, the uniform bump was obtained by means of removing impurities in the plating solution. Consequently the resultant solder bump was obtained in an optimal current density of the range of $1A/dm^2$ to $15A/dm^2$, which has acceptable bump shape and surface roughness with 12inch wafer trial results.