• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1989년도 하계종합학술대회 논문집
• /
• pp.359-363
• /
• 1989

Recently, it is reported that the behavior of thermal $SiO_2$ under high electric field and current condition has a major effect on MOS device degration. Furthermore, when thin oxide films are applied in practical device, the presence of oxide defects will be a serious problem. In this paper, because TDDB is the useful method to measure the effective density of defects, we stressed MOS structure that is 150 A of thermally grown $SiO_2$as a function of electric field (9-19 MV/cm), temperature ($22^{\circ}C$ - $150^{\circ}C$) and current. By examing TDDB under positive voltage, long-term oxide breakdown reliabiliy is described. From these data, breakdown wearout limitation for the oxide films can be characterized.

• 전자공학회논문지A
• /
• 제33A권6호
• /
• pp.136-143
• /
• 1996

A simple analytic model for the planar junctions with multiple foating field limiting rings(FLR) is presented which yields analytic expressions for the breakdown voltage and optimum ring spacings. the normalized potential of each ring is derived as a function of the normalized depletion width and the ring spacing. Based on the assumption that the breakdwon occurs simulataneously at cylindrical junctions of FLR structure where the peak sruface electric fields are equal, the optimum ring spacings are determined. The resutls are in good agreement with the simulations obtained from two dimensional device simulation program MEDICI and with the experimental data reported. The normalized experessions allow a calculation of breakdown voltage and optimum spacing over a broad range of junction depth and background doping levels.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1997년도 추계학술대회 논문집 학회본부
• /
• pp.379-381
• /
• 1997

The dielectric layers in AC plasma display panel(AC PDP) are essential to the discharge cell structure, because they protect metal electrodes from sputtering by positive ion and from a sheath of wall charges which are essential to memory function of AC PDP. Furthermore, this layer should be transparent because the visible light must pass through the layer. In this paper, the dielectric breakdown strength and transparency of the dielectric layer on the discharge electrodes are studied. The variables in this test are the dielectric layer thickness, dielectric firing condition, gas pressure, species of gas and so on.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1997년도 하계학술대회 논문집 C
• /
• pp.1286-1288
• /
• 1997

In this study, partially-depleted SOI MOSFET with multi-gate was fabricated on p-type SIMOX(Seperation by Implanted Oxygen). As increase the number of its gate, increase the breakdown voltage. But kink effect was not affected by the number of its gate. However, it is known that the asymmetric gate structure reduce kink effect. So if asymmetric multi-gate applied to partially-depleted SOI MOSFET, it is expected that the breakdown voltage of SOI MOSET with asymmetric multi-gate is higher than that of SOI MOSFET with single gate and that kink effect is reduced by SOI MOSFET with asymmetric multi-gate.

• ETRI Journal
• /
• 제28권2호
• /
• pp.253-256
• /
• 2006

We propose a novel power metal oxide semiconductor field effect transistor (MOSFET) employing a strained-Si channel structure to improve the current drivability and on-resistance characteristic of the high-voltage MOSFET. A 20 nm thick strained-Si low field channel NMOSFET with a $0.75\;{\mu}m$ thick $Si_{0.8}Ge_{0.2}$ buffer layer improved the drive current by 20% with a 25% reduction in on-resistance compared with a conventional Si channel high-voltage NMOSFET, while suppressing the breakdown voltage and subthreshold slope characteristic degradation by 6% and 8%, respectively. Also, the strained-Si high-voltage NMOSFET improved the transconductance by 28% and 52% at the linear and saturation regimes.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 1997년도 추계학술대회 논문집
• /
• pp.225-228
• /
• 1997

The main fault in this interface is that power cable insulating materials are mainly composed of a double layered structure, XLPE/FPDM laminates in cable joint. In this parer, we instituted the interface of XLPE/EPDM laminates and then investigated the breakdown and conduction characteristics as a function of heat treatment time. The results showed that conduction current was influenced by volatile crosslinking by-products which remained inside the insulating material during the production of XLPE and EPDM, especially during heat treatment process. And conduction current of XLPE/Oil 12500cSt/EPDM was more stable than XLPE/Grease/EPDM from the long heat treatment time. AC breakdown strength of silicone oil itself from the heat treatment was changed during the 4∼12 hour heat treatment time.

• Transactions on Electrical and Electronic Materials
• /
• 제1권4호
• /
• pp.16-19
• /
• 2000

Power transistors to be used in Power Integrated Circuits(PIC) are required to have low on resistance, fast switching speed, and high breakdown voltage. The lateral IGBTs(LIGBTs)are promising power devices for high voltage PIC applications, because of its superior device characteristics. In this paper, dual cathode LIGBT(DCIGBT) for high voltage is presented. We have verified the effectiveness of high blocking voltage in the new device by using two dimensional devices simulator. We have analyzed the forward blocking characteristics , the latch up performance and turn off characteristics of the proposed structure. Specially, we have focused forward blocking of LIGBT. The forward blocking voltage of conventional LIGBT and the proposed LIGBT are 120V and 165V, respectively. . The forward blocking characteristics of the proposed LIGBT is better than that of the conventional LIGBT. This forward blocking comparison exhibits a 1.5 times improvement in the proposed LIGBT.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1998년도 추계학술대회 논문집 학회본부A
• /
• pp.70-72
• /
• 1998

Because of using PWM inverters and converters. The problems of insulation breakdown is emerging in both high voltage motors and general motors. In conventional methods, the viewpoint of surge problems is wave propagation with or without cable and inverter. For the purpose of knowing the situation of insulation breakdown, the end-turn coil of windings in the motor winding insulation structure is modelled by FEM, and field analysis of that is done. For first step, only end-turn coil is modelled and the model is simulated with FEM by approximating the resistivity of metallic foil surrounding insulation layers with having nonlinear property. Next, the result of simulation with nonlinear resistivity are compared with the result of linear resistivity. Because of microscope analysis, there is the problem of generalization but the situation of corona discharge in end-turn coil will be explained from this simulation.

• Preventive Nutrition and Food Science
• /
• 제6권4호
• /
• pp.253-256
• /
• 2001

Irradiation of food is not only used for sanitation purposes but can be used for processing techniques to reduce or eliminate toxic or undesirable compounds on food. Irradiation wag effective to reduce the allergenicity of food by modification of the structure of proteins causing allergy reactions. Volatile N-nitrosmaine was reduced or eliminated by irradiation in the model system study and the breakdown products by irradiation did not recombine under human stomach conditions (pH 2,3, and 4,37$^{\circ}C$). The possibility of residual chlorophyll b reduction by irradiation was also found, and the model study indicated that irradiation be used to destroy chlorophyll b, resulting in protection from photooxidation in oil without acceleration of lipid oxidation during irradiation. In this paper, several on-going research projects for the application of food irradiation as a new processing technique are introduced, including reduction of food allergens, breakdown of volatile N-nitrosamine and residual chlorophyll b.

• 대한전자공학회논문지SD
• /
• 제48권12호
• /
• pp.8-14
• /
• 2011

본 논문에서는 이차원 소자 시뮬레이션을 활용하여 주어진 게이트-드레인 간격에서 AlGaN/GaN-on-Si HEMT (high electron mobility transistor) 의 고항복전압 구현을 위한 게이트 전계판의 최적화 구조를 제안하였다. 게이트 전계판 구조를 도입하여 게이트 모서리의 전계를 감소시켜 항복전압을 크게 증가시킬 수 있음을 확인 하였으며, 이때 전계판의 길이와 절연막의 두께에 따라 게이트 모서리와 전계판 끝단에서 전계분포의 변화를 분석하였다. 최적화를 위하여 시뮬레이션을 수행한 결과, 1 ${\mu}m$ 정도의 짧은 게이트 전계판으로도 효과적으로 게이트 모서리의 전계를 감소시킬 수 있으며 전계판의 길이가 너무 길어지면 전계판과 드레인 사이의 남은 길이가 일정 수준 이하로 감소되어 오히려 항복전압이 급격하게 감소함을 보였다. 전 계판의 길이가 1 ${\mu}m$ 일 때 최대 항복전압을 얻었으며, 게이트 전계판의 길이를 1 ${\mu}m$로 고정하고 $SiN_x$ 박막의 두께를 변화시켜본 결과 게이트 모서리와 전계판 끝단에서의 전계가 균형을 이루면서 항복전압을 최대로 할 수 있는 최적의 $SiN_x$ 박막 두께는 200~300 nm 인 것으로 나타났다.