• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1924-1937
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• 1996

In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

• Journal of Power System Engineering
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• v.17 no.4
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• pp.72-78
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• 2013

Compacted graphite iron 340 was carried out the heat treatment from 873 to 1,273 K. Compacted graphite iron 340 was evaluated relationship between the sound velocity, the attenuation coefficient and the tensile strength. The obtained results are as following. The signal strength of C scan images were weak according to increasing of heat treatment temperature and time. The amplitude of A scan and B scan was also low. This can be cause that the graphite was grown into the type of vermicular, and the many of grain boundary with ultrasound scattering were increase. The sound velocity was depend upon the heat treatment temperature and time, the attenuation coefficient had nothing to do with the temperature and time. The higher the heat treatment temperature, the tensile strength and the sound velocity were decreased. However, the tensile strength was proportional to the sound velocity. The higher tensile strength, the faster the sound velocity.

• The Magazine of the IEIE
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• v.22 no.12
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• pp.93-104
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• 1995

디지탈 회로를 구현한 칩 및 보드의 시험 비용을 줄이기 위하여 사용되는 스캔 설계 기술 동향에 대하여 기술하였다. 스캔 설계 기술은 칩 수준에서 먼저 적용되기 시작하였다. 회로의 모든 플립플롭을 스캔할 수 있도록 하는 완전 스캔이 먼저 개발되었고, 최근에는 플립플롭의 일부분만 스캔할 수 있도록 하는 부분 스캔 기술이 활발하게 논의되고 있다. 한편 보드의 시험에 있어서도 보드에 실장되는 칩의 밀도가 증가되고, 표면 실장 기술이 일반화됨에 따라 종래의 시험 기술로는 충분한 시험을 거치는 것이 불가능하게 되었다. 따라서, 칩에 적용되던 기법과 유사한 스캔 설계 기술이 적용되기 시작하였다. 이를 경계 스캔(Boundary Scan)이라고 하는데, 이 기술은 80년대 후반부터 본격적으로 논의되기 시작하였다. 1990년에는 이 기술과 관련된 IEEE의 표준이 제정되어 더욱 많이 적용되는 추세에 있다. 이 논문에서는 이러한 칩 및 보드의 시험을 쉽게하기 위한 스캔 설계 기법의 배경, 발전 과정 및 기술의 내용을 소개한다.

• Journal of Biosystems Engineering
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• v.17 no.2
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• pp.143-155
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• 1992

The aim of this study is to develop a general purpose algorithm for analyzing geometrical features of agricultural products and microscopic particles regardless of their numbers, shapes and positions with a computer vision system. Primarily, boundary informations of an image were obtained by Scan Line Coding and Scan & Chain Coding methods and then with these informations, geometrical features such as area, perimeter, lengths, widths, centroid, major and minor axes, equivalent circle diameter, number of individual objects, etc, were analyzed. The algorithms developed in this study was evaluated with test images consisting of a number of randomly generated ellipsoids or a few synthesized diagrams having different features. The result was successful in terms of accuracy.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.11B
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• pp.1957-1965
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• 2000

본 논문에서는 휴대 멀티미디어 응용을 위한 MDSP(Multimedia Fixed Point DSP) 칩의 내장 메모리 테스트와 기판 수준의 테스트를 지원하기 위해 내장 메모리 테스트를 위한 자체 테스트 기법, 기판 수준의 테스트 지원 및 내장 메모리를 위한 자체 테스트 회로를 제어하기 위한 경계 주사 기법을 구현하였다. 본 논문에서 구현한 기법들은 Verilog HDL을 이용하여 회로들을 설계하였으며, Synopsys 툴과 현대 heb60 라이브러리를 이용하여 합성하였다. 그리고 회로 검증을 위한 시뮬레이터는 Cadence사의 VerilogXL을 사용하였다.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.795-798
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• 1998

IEEE1149.1 바운다리스캔은 칩과 칩간의 연결선상에서 발생가능한 지연고장을 점검 할 수 없게 설계되어있다. 칩에서 패턴을 주입하는 UpdateDR과 연결선을 통해서 전달된 결과 값을 관측하는 captureDR간의 간격이 ITCK가 되도록 UPdaeDR을 변경하는 기술보다 동작속도 및 추가영역면에서 최적임을 보여준다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.9
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• pp.114-120
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• 1995

It is important to test the various kinds of interconnect faults between chips on a card/module. When boundary scan design techniques are adopted, the chip to chip interconnection test generation and application of test patterns is greatly simplified. Various test generation algorithms have been developed for interconnect faults. A new interconnect test generation algorithm is introduced. It reduces the number of test patterns by half over present techniques. It also guarantees the complete diagnosis of mutiple interconnect faults.

• Korean Journal of Computational Design and Engineering
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• v.10 no.3
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• pp.162-167
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• 2005

A 3D solid element mesh generation algorithm was newly developed. 3D surface points of global rectangular coordinates were supplied by a 3D laser scanner. The algorithm is strait forward and simple but it generates hexahedral solid elements. Then, the surface rectangular elements were generated from the solid elements. The key of the algorithm is elimination of unnecessary elements and 3D boundary surface fitting using given 3D surface point data.

• Proceedings of the Korea Society for Industrial Systems Conference
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• 2001.05a
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• pp.209-216
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• 2001

A key advantage of boundary scan technology is the ability to observe data at device inputs and control data at device outputs, independent of on-chip system logic. But, this method has a disadvantage for detecting of faults that changes their states very fast. We present a method to solve this problem and make it possible to detect the signals. We shown the simulation results of testing a circuit that has fast signal above the clock speed.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04b
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• pp.1635-1638
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• 2002

IEEE Std.1149.1 표준의 제정으로 경계주사는 규격화되었다. 그러나 이러한 표준의 제정에도 불구하고 실제 보드 테스트를 수행하는 데에는 아직도 많은 어려움을 가지고 있다. 본 연구에서는 IEEE Std.1149.1의 표준을 만족하면서도 기존의 방법보다 안전성에서 우위를 보임과 동시에 보다 높은 고장 검출률을 가지는 경계주사 테스트 시스템의 새로운 구현 기법을 제시한다.