• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.230-231
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• 2014

Compressive sensing is a new sampling technique, which allows to sample a signal under the Nyquist-Shannon sampling rate. For block-based compressive sensing, a hybrid sensing matrix which contains low-frequency patterns in addition to the random Gaussian numbers is good for exploiting typical property of natural images. By noting that MH-BCS-SPL is well known for its good recovery performance, this paper investigates effect of the hybrid sensing matrix on MH-BCS-SPL in the sense of how large portion of low-frequency patterns can provide performance improvement.

• International Journal of Aeronautical and Space Sciences
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• v.4 no.2
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• pp.37-50
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• 2003

A next generation small satellite HAUSAT-1, the first picosatellite developed in Korea, is being developed as one of the international CubeSat program by Space System Research Lab. of Hankuk Aviation University. A fault-tolerant incremental design methodology has been addressed in this paper. In this study, the effect of system redundancy on reliability was in details analyzed in accordance with the implementation of fault-tolerant system. Four different system recovery levels are proposed for HAUSAT-1 fault-tolerant system optimization. As a result, the HAUSAT-1 fault-tolerant system architecture design and reliability analysis has acquired about 11% reliability improvement.

• Journal of Industrial Technology
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• v.24 no.A
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• pp.139-155
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• 2004

A room and pillar mining method has been adopting at the Jeungsun limestone mine. To check stability of pillar with multiple and irregular openings, the size, shape and spacing of rib pillar were first designed using some empirical suggestions. The Finite Difference Method(FDM)was used to analyze the pillar stability. Twelve different cases with the variation of K(horizontal/vertical stress)values, different height and different spacing of pillar were used in this study. Finally Mohr-Coulomb criterion was adopted to calculate the safety factors. Horizontal and vertical displacement, maximum and minimum principal stresses, range of plastic zone and safety factors were calculated at each case. As a result of analysis, the size of one block is 160m long, 70m wide, 40m high with 20m wide rib pillar and 20m square column pillar. The overall recovery at this case can be estimated about 40%.

• Proceedings of the Korea Concrete Institute Conference
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• 2006.05b
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• pp.321-324
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• 2006

The latest concrete has showed that the deterioration of durability has been increased by the damage from salt, carbonation, freezing & thawing and the others. Therefore, it is needed to protect durability and performance according to the appropriate materials and methods in the concrete structures. In general, several types of polymer and silicate are used as protecting deterioration agents of concrete structures, but these agents have many problems because of low durability and properties. In this study, It developed the deterioration restraining agent using polycondensed silicate and monomer that can block a deterioration cause such as CO2 gas, salt and water from the outside and enhance waterproofing ability by reinforcing the concrete surface when applying it to concrete structures. Also, it evaluated improving concrete performance using a deterioration restraining agent.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.413-418
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• 1987

The software developed for the large scale Programmable Controller consists of the programmer's S/W, the Controller's S/W the RBC's (Remote Base Controller's) S/W and the Analog's S/W. The programmer's S/W, running on the Programmer, includes the editor, the compiler, the communication program, and some other programs for easy use. The Controller S/W, which requires the fast scanning time, consists of the BTI( Block Type Instruction) solving program, the timer service routine, the i/o update program, the communication program and etc. The RBC's S/W includes the communication program, the error recovery program and the i/o processing program. The analog S/W, controlled by the Programmer, includes the PID program. The data communication between the Programmer and the Controller the Controller and the RBC, and the RBC and the Analog are developed.

• Journal of Advanced Navigation Technology
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• v.16 no.2
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• pp.211-218
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• 2012

In this paper, we propose a fault injection attack on AES-CMAC, which is defined by IETF. The fault assumption used in this attack is based on that introduced at FDTC'05. This attack can recover the 128-bit secret key of AES-CMAC by using only small number of fault injections. This result is the first known key recovery attack result on AES-CMAC.

• 한국정보통신설비학회:학술대회논문집
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• 2005.08a
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• pp.154-158
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• 2005

In this paper, we design optical receiver composed of CDR(clock and data recovery), SA(sense amp), TIA(transimpe dence amplifier), and decision circuit. The optical receiver can be classified to two main block, one is Deserializer composed of CDR and SA, another is PD receiver composed of preamplifier(샴), peak detector, etc. In this paper, we propose CDR using delayed data topology that could improve defects of existing CDR. The optical receiver that is proposed in this paper has the role of translation a 1.25 Gb/s optical signal to $10{\times}125 Mb/s$ array electric signals. This optical receiver is verified by simulator(hspice) using 0.35 um CMOS technology.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06c
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• pp.72-74
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• 2012

최근 스마트폰, 태블릿이 보편화되고 플래시 메모리가 모바일기기의 저장장치로 많이 사용되면서 저장되는 데이터에 대한 보안성도 높아지고 있다. 모바일 기기를 사용하는 사용자 입장에서 더 이상 필요치 않은 목적으로 데이터를 삭제하고 유출을 막기 위해 파일 와이핑 기법을 사용한다. 하지만 일반적인 와이핑 기법은 하드디스크 특성을 바탕으로 수행되기 때문에 플래시 메모리를 사용할 경우 플래시 메모리 특성으로 인해 와이핑 이후 기존정보가 존재하기 때문에 복구가 가능하다. 최근 플래시 메모리 데이터의 보안성을 요구하는 기법이 연구된바 있지만 불필요한 오버헤드 및 기법 적용이 제한적이라는 문제가 있다. 본 논문에서는 다양한 FTL에 적용이 가능한 플래시 메모리상의 저장된 데이터에 대한 와이핑 수행이후 복구 방지 기법을 제안한다. 이 기법은 임의 값을 이용한 블록 치환 알고리즘을 통해 테이블을 생성하고 테이블을 이용해서 플래시 메모리를 블록 단위로 치환을 하여 수행한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2019.05a
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• pp.522-524
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• 2019

In spite of a rapid development in the quality of built-in mobile cameras, their some physical restrictions hinder them to achieve the satisfactory results of digital single lens reflex (DSLR) cameras. In this work we propose an end-to-end deep learning method to translate ordinary images by mobile cameras into DSLR-quality photos. The method is based on the framework of generative adversarial networks (GANs) with several improvements. First, we combined the U-Net with DenseNet and connected dense block (DB) in terms of U-Net. The Dense U-Net acts as the generator in our GAN model. Then, we improved the perceptual loss by using the VGG features and pixel-wise content, which could provide stronger supervision for contrast enhancement and texture recovery.