• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1869-1871
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• 2004

The primary role of ZnO arresters is to protect transmission and distribution equipments against lightning surges. The extremely nonlinear V-I characteristics of the ZnO arrester obviates the need for isolation gaps and consequently it is continuously connected to line voltage. For this reason, ZnO arresters are degraded with increasing with time in actual power systems. In this work, the characteristics of the luminous events between the ZnO block and electrodes were investigated. As a result, the luminous events were effected by the impulse and the near polarity of the luminous event was intense near the grounded electrode. Also the luminous event may cause the degradation of ZnO arrester block.

• Proceedings of the KIEE Conference
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• 2004.11a
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• pp.26-28
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• 2004

The primary role of ZnO arresters is to protect transmission and distribution equipments against lightning surges. The extremely nonlinear V-I characteristics of the ZnO arrester obviates the need for isolation gaps and consequently it is continuously connected to line voltage. For this reason, ZnO arresters are degraded with time in actual power systems. In this work, the characteristics of the luminous events caused between the ZnO block and electrodes according to the electrode area were investigated. As a result, the luminous events were effected by electrode area and the longer electrode areas were increased, the more luminous events were decreased. Also the reduction of luminous events was fumed up to the degraded ZnO arrester block.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.451-462
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• 2009

Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

• Proceedings of the Korea Information Processing Society Conference
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• 2011.11a
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• pp.30-32
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• 2011

현재 컴퓨터 시스템에서 대표적인 성능 저하가 발생되는 부분은 블록 I/O 시스템이다. 안드로이드와 같은 모바일 장치 또한 위와 같은 성능 이슈를 가지고 있다. 본 논문에서는 리눅스 블록 레이어의 I/O를 tracing 해주는 blktrace를 안드로이드 장치에 적용하여 SQLite를 사용하는 Web Browsing 시의 I/O 패턴 분석과 성능 개선 방안을 제시 한다.

• Journal of the Korean Ceramic Society
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• v.49 no.3
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• pp.205-215
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• 2012

It has been studied the crystal and block structures of the hexagonal ferrites with M, W, Y and Z types prepared by various coprecipitation-oxidation method. The structures have been refined with a Rietveld analysis of the powder X-ray diffraction pattern with high precision ($R_{WP}$ <0.09, $R_I$ <0.03). The density difference between the S-blocks was proportioned to the cobalt contents in hexagonal ferrites, but that between the R or T-blocks was relatively small. Compared with the blocks and cation-oxygen polyhedra in BaM ($BaFe_{12}O_{19}$), those were bulky to the normal direction for the c-axis in $Co_2W$ ($BaCo_2Fe_{16}O_{27}$) and to the parallel direction for the c-axis in $Co_2Y$ ($Ba_2Co_2Fe_{12}O_{22}$) and $Co_2Z$ ($Ba_3Co_2Fe_{24}O_{41}$). The S-blocks of $Co_2W$, $Co_2Y$, and $Co_2Z$ were unstable and distorted. Because the T-block of $Co_2Z$ was unstable, the T-block was decomposed into the Ba-rich phase and $Co_2W$ at high temperatures above $1200^{\circ}C$. A standard powder X-ray diffraction pattern for $Co_2Z$ was proposed as well.

• International Journal of Internet, Broadcasting and Communication
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• v.13 no.2
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• pp.27-35
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• 2021

NAND flash memory-based SSD needs an internal software, Flash Translation Layer(FTL) to provide traditional block device interface to the host because of its physical constraints, such as erase-before-write and large erase block. However, because useful host-side information cannot be delivered to FTL through the narrow block device interface, SSDs suffer from a variety of problems such as increasing garbage collection overhead, large tail-latency, and unpredictable I/O latency. Otherwise, the new type of SSD, open-channel SSD exposes the internal structure of SSD to the host so that underlying NAND flash memory can be managed directly by the host-level FTL. Especially, I/O data classification by using host-side information can achieve the reduction of garbage collection overhead. In this paper, we propose a new scheme to reduce garbage collection overhead of open-channel SSD by separating the journal from other file data for the journaling filesystem. Because journal has different lifespan with other file data, the Write Amplification Factor (WAF) caused by garbage collection can be reduced. The proposed scheme is implemented by modifying the host-level FTL of Linux and evaluated with both Fio and Filebench. According to the experiment results, the proposed scheme improves I/O performance by 46%~50% while reducing the WAF of open-channel SSDs by more than 33% compared to the previous one.

• The Journal of Korean Association of Computer Education
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• v.6 no.3
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• pp.1-8
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• 2003

In this paper, I proposed a sort algorithm named Information Block Sort Algorithm(IBSAl which is not influenced on distribution of data in the list and has time complexity of O(NlogN). Also I evaluated the IBSA using a simulator. Performance analysis shows that, in case of sorting randomly generated two millions data, the number of actual comparisons has taken place about 36% of the number of comparisons in the improved Quick sort algorithm and 22% in Quick sort algorithm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.110-119
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• 1996

A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

• Polymer(Korea)
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• v.32 no.3
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• pp.239-245
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• 2008

Block copolymers of the general formula $[(-CO-R'-CO-HN-Ar-NH-CO-R'-CO)_xNH(CH_2)_3-(Me_2SiO)_y(CH_2)_3NH_2]_n$, [n=18.00 to 1175.0] where $R'=CH_2CH(CH_2GeCl_3)$;$CH_2CHGeCl_3CH_2$; and $Ar=-C_6H_4$;$-(o.CH_3C_6H_4)_2$;$-o.CH_3OC_6H_4)_2$;$-(o.CH_3C_6H_4)$ were prepared by a polycondensation reaction of polyamide containing a pendant trichlorogermyl group and terminal acid chloride $Cl(-CO-R'-CO-NH-Ar-NH-CO-R'-CO-)_xCl$ with aminopropyl-terminated polydimethylsiloxane $H_2N(CH_2)_3(Me_2SiO)_y-(CH_2)_3NH_2]$, (PDMS). These polymers were characterized by elemental analysis, $T_g$, FT-IR, $^1H$-NMR, solid state $^{13}C$-NMR, and molecular weight determination. The thermal stability of these copolymers was examined using thermal analysis techniques, such as TGA and DSC. Their molecular weights as determined by laser light scattering technique ranged $5.13{\times}10^5$ to $331{\times}10^5\;g/mol$. These polymers display their $T_g$ in the range of 337 to $393^{\circ}C$ with an average decomposition temperature at $582^{\circ}C$.

• International journal of advanced smart convergence
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• v.9 no.3
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• pp.253-259
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• 2020

Most of today's large-scale cloud systems and enterprise data centers are distributing resources to improve scalability and resource utilization. NVMe-over-Fabric protocol allows submitting NVMe commands to a remote NVMe SSD through RDMA (Remote Direct Memory Access) network. It is attracting attention recently because it is possible to construct a disaggregation storage system with low latency through the protocol. However, the current I/O stack of NVMe-over-Fabric has an inefficient structure for maintaining compatibility with the traditional I/O stack. Therefore, in this paper, we propose a new mechanism to reduce I/O latency and CPU overhead by modifying I/O path of NVMe-over-Fabric to pass through legacy block layer. According to the performance evaluation results, the proposed mechanism is able to reduce the I/O latency and CPU overhead by up to 22% and 24% compared to the existing NVMe-over-Fabrics protocol, respectively.