• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.7
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• pp.42-49
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• 1993

In this paper, switched-capacitor building block presented which are suitable for implementation in GaAs MESFET technology. They include a current source, a gain stage, and an operational amplifier. Switched-capacitor design techniques are discussed that minimize filter sentsitivity to finite gain of the GaAs operational amplifier. Simulation results are presented on third-order elliptic lowpass ladder filter at a sampling rate of 5GHz.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.9 no.2
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• pp.56-67
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• 2010

Optical fiber subscriber receive communication system is a core technology of multimedia home networks because it provides the high-level quality of data and services. This paper executes an analysis and research on this communication systems and presents the theoretical background for the purpose of understanding the optical communication system principal and explaining signal process flows to divide each block for the implementing ASIC design.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.56-59
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• 1997

Vision system is mainly consist of three parts of perception, action. One of these parts, perception system detects visual target in surrounding environment. Block-based motion estimation with compensation is one of the popular approaches without accuracy. The hierarchical method the optical flow with gradient is used to improve optical flow time delay.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.911-914
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• 2000

본 논문에서는 배터리가 없는 ASK 전송방식의 RFID(Radio Frequency IDentification) Transponder 칩 설계에 관한 내용을 다룬다. Transponder IC는 power-generation 회로, clock-generation 회로, digital block, modulator, overoltge protection 회로로 구성된다. 설계된 칩은 저전력 회로를 적용하여 원거리 transponder칩을 구현할 수 있도록 하였다. 설계된 회로는 0.25㎛ 표준 CMOS 공정으로 레이아웃하여 제작하였다.

• Proceedings of the KSME Conference
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• 2005.11a
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• pp.181.1-181.1
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• 2005

• Proceedings of the Korea Multimedia Society Conference
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• 2012.05a
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• pp.431-431
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• 2012

• The Korean Journal of Applied Statistics
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• v.12 no.1
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• pp.253-260
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• 1999

이어진 블록계획 중에서 대칭 균형된 불완비 블록계획(Symmetrical Balanced Incomplete Block Design : SBIBD)을 이용하여 n-ary를 블록 완전이면교배(Complete Diallel Cross : CDC)계획을 설계하였다. 처리 수와 반복 수가 고정된 경우, 이렇게 설계된 계획이 균형된 불완비 블록계획을 이용해서 설계한 계획들 중에서 가장 효율이 높은 계획임을 보인다.

• International Journal of High-Rise Buildings
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• v.10 no.3
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• pp.243-250
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• 2021

Y

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.1
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• pp.79-85
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• 2005

In this paper, low-power design and implementation techniques for IMT-2000 interpolation filter are proposed. Processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized for low-power implementation. proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of filter coefficient. Finally, in third shift register block, multiplied values are output and stored in shift register. For IMT-2000 interpolation filter, proposed and conventional structures are implemented by using Verilog-HDL coding. Gate counts for the proposed structure is reduced to 31.57% comparison with those of the conventional one.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.81-90
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• 2004

The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.