• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.446-457
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• 2017

In order to reduce the size of frame memory or bus bandwidth, frame memory compression (FMC) recompresses reconstructed or reference frames of video codecs. This paper proposes a novel FMC design based on discrete wavelet transform (DWT) - set partitioning in hierarchical trees (SPIHT), which supports fine-scalable throughput and is area-efficient. In the proposed design, multi-cores with small block sizes are used in parallel instead of a single core with a large block size. In addition, an appropriate pipelining schedule is proposed. Compared to the previous design, the proposed design achieves the processing speed which is closer to the target system speed, and therefore it is more efficient in hardware utilization. In addition, a scheme in which two passes of SPIHT are merged into one pass called merged refinement pass (MRP) is proposed. As the number of shifters decreases and the bit-width of remained shifters is reduced, the size of SPIHT hardware significantly decreases. The proposed FMC encoder and decoder designs achieve the throughputs of 4,448 and 4,000 Mpixels/s, respectively, and their gate counts are 76.5K and 107.8K. When the proposed design is applied to high efficiency video codec (HEVC), it achieves 1.96% lower average BDBR and 0.05 dB higher average BDPSNR than the previous FMC design.

• Journal of the Korean Home Economics Association
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• v.43 no.8 s.210
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• pp.69-81
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• 2005

The purpose of this study is to design high school boy's uniforms, which fit well and express the traditional aesthetics of Korean clothing. Korean traditional clothing is getting ground for the use as active wear as well as formal wear such as wedding or special holiday clothing. This is partly due to the introduction of western clothing in Korea because of the practical nature of this type of clothing. This study was carried out as follows: 1. First, 197 high school boys from 5 different high schools were surveyed. All of these schools use Korean style school uniforms. The survey asked the students about their satisfaction with the current designs, problems and design preferences for Korean style high school uniforms. In general, the boys are not satisfied with the aesthetic and fashionable aspects of their uniforms. 2. The second survey dealt with design preferences from a variety of design options of Korean-style school uniforms. The design options were presented to the students as in the form of 10 different types jackets and 6 different types of pants. Using the results of the second survey as a guideline, the designs of Korean style school uniforms were developed. 3. In order to make the test garments, a block bodice pattern for the Korean style school uniforms was developed. Using the developed bodice block pattern, 6 designs were made of wool. The 6 test designs consisted of 3 different types of jackets and 3 different types of pants. 4. Incorporating the most preferred design features, school boy Korean style school uniform designs were developed. The characteristics of the design include neck line opening and its finishing, AH and sleeve shape, embroidered traditional patterns and fastenings. In this study we were able to develop comfortable clothing, which expressed the traditional aesthetics of Korean clothing.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.5
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• pp.681-688
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• 2018

As environmental regulations have been strengthened and high fuel efficiency has been in demand in recent years, the number of ships using natural gas as a fuel is increasing. The demand for ships using LPG or methanol, which are emerging as eco-friendly vessel fuels, is also increasing. In this perspective, ME-LGI engines using LPG or methanol as a fuel have attracted considerable attention. Ships equipped with an ME-LGI engine are required to check the reliability of the fuel injection valve during shipping. This means that the development of a fuel injection valve tester is essential for the commercialization of ME-LGI engine. This study conducted the conceptual design of a fuel injection valve tester for ME-LGI engines using a system engineering process in the order of requirements analysis, functional analysis, and design synthesis. In the requirement analysis stage, the operating process of fuel injection valve was analyzed, and the necessity of checking the sealing oil leakage was then derived. In the functional analysis stage, the functions and flow of them were defined at each functional level. In the design synthesis stage, the equipment for each function was set and the process block diagram based on it was derived. In addition, preliminary risk analysis was performed as a part of system analysis and control, and safety measures were added to the conceptual design. This study is expected to be a good reference material for the concept design of other systems in the future because it shows the application process of a system engineering process to the conceptual design in detail.

• Proceedings of the Korea Committee for Ocean Resources and Engineering Conference
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• 2000.04a
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• pp.189-194
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• 2000

Due to the rapid growth of ship building industry and increment of ship construction in Korea, several hundred thousand of lifting lugs per year, have been installed at the lifting positions of ship block and removed after finishing their function, therefore, appropriate design system for strength check or optimal design of each lug structure has been required in order to increase the capability of efficient design. In this study, design system of D-type lifting lug structure which is most popular and useful in shipyards, was developed for the purpose of initial design of lug structure. Developed system layout and graphic user interface for this design system based on the C++ language were explained step by step. Using this design system, more efficient performance of lug structural design will be expected on the windows of personal computer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.15-22
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• 2005

This paper proposes an efficient structure which is able to perform self-detection and self-repair for faults in a digital system by imitating the structure of living beings. The self-repair system is composed of artificial cells, which have homogeneous structures in the two-dimension, and spare cells. An artificial cell is composed of a logic block based on multiplexers, and a genome block, which controls the logic block. The cell is designed using DCVSL (differential cascode voltage switch logic) structure to self-detect faults. If a fault occurs in an artificial cell, it is self-detected by the DCVSL. Then the artificial cells which belong to the column are disabled and reconfigured using both neighbour cells and spare cells to be repaired. A self-repairable 2-bit up/down counter has been fabricated using Hynix $0.35{\mu}m$ technology with $1.14{\times}0.99mm^2$ core area and verified through the circuit simulation and chip test.

• Journal of IKEEE
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• v.22 no.1
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• pp.38-45
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• 2018

An integrated cryptographic processor that efficiently integrates ARIA, AES block ciphers and Whirlpool hash function into a single hardware architecture is described. Based on the algorithm characteristics of ARIA, AES, and Whirlpool, we optimized the design so that the hardware resources of the substitution layer and the diffusion layer were shared. The round block was designed to operate in a time-division manner for the round transformation and the round key expansion of the Whirlpool hash, resulting in a lightweight hardware implementation. The hardware operation of the integrated ARIA-AES-Whirlpool crypto-processor was verified by Virtex5 FPGA implementation, and it occupied 68,531 gate equivalents (GEs) with a 0.18um CMOS cell library. When operating at 80 MHz clock frequency, it was estimated that the throughputs of ARIA, AES block ciphers, and Whirlpool hash were 602~787 Mbps, 682~930 Mbps, and 512 Mbps, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.9
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• pp.1993-1999
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• 2011

This paper describes a design of area-efficient/low-power cryptographic processor for HIGHT block cipher algorithm, which was approved as standard of cryptographic algorithm by KATS(Korean Agency for Technology and Standards) and ISO/IEC. The HIGHT algorithm, which is suitable for ubiquitous computing devices such as a sensor in USN or a RFID tag, encrypts a 64-bit data block with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we optimize round transform block and key scheduler to share hardware resources for encryption and decryption. The HIGHT64 core synthesized using a 0.35-${\mu}m$ CMOS cell library consists of 3,226 gates, and the estimated throughput is 150-Mbps with 80-MHz@2.5-V clock.

• The Journal of the Korea Contents Association
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• v.16 no.10
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• pp.514-521
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• 2016

The High Efficiency Video Coding (HEVC) standard provides superior coding efficiency by utilizing highly flexible block structure and more diverse coding modes. However, rate-distortion optimization (RDO) process for the decision of optimal block size and prediction mode requires excessive computational complexity. To alleviate the computation load, this paper proposes a new moment-based fast CU size decision algorithm for intra coding in HEVC. In the proposed method, moment values are computed in each CU block to estimate the texture complexity of the block from which the decision on an additional CU splitting procedure is performed. Unlike conventional methods which are mostly variance-based approaches, the proposed method incorporates the third-order moments of the CU block in the design of the fast CU size decision algorithm, which enables an elaborate classification of CU types and thus improves the RD-performance of the fast algorithm. Experimental results show that the proposed method saves 32% encoding time with 1.1% increase of BD-rate compared to HM-10.0, and 4.2% decrease of BD-rate compared to the conventional variance-based fast algorithm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.6
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• pp.8-16
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• 2003

Aerodynamic characteristics over Micro Aerial Vehicle(MAV) in low Reynolds number regime are numerically studied using 3-D unsteady, incompressible Navier-Stokes flow solver with single partitioning method for multi-block grid. For more efficient computation of unsteady flows, this flow solver is parallel-implemented with MPl(Message Passing Interface) programming method. Firstly, MAV wing with not complex geometry is considered and then, we analyze aerodynamic characteristics over full MAV configuration varying the angle of attack. Present computational results show a better agreement with the experimental data by MACDL(Micro Aerodynamic Control and Design Lab.), Seoul National University. We can also find the conceptually designed MAV by MACDL has the static stability.