• Title/Summary/Keyword: block design

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FPGA-Based Post-Quantum Cryptography Hardware Accelerator Design using High Level Synthesis (HLS 를 이용한 FPGA 기반 양자내성암호 하드웨어 가속기 설계)

  • Haesung Jung;Hanyoung Lee;Hanho Lee
    • Transactions on Semiconductor Engineering
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    • v.1 no.1
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    • pp.1-8
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    • 2023
  • This paper presents the design and implementation of Crystals-Kyber, a next-generation postquantum cryptography, as a hardware accelerator on an FPGA using High-Level Synthesis (HLS). We optimized the Crystals-Kyber algorithm using various directives provided by Vitis HLS, configured the AXI interface, and designed a hardware accelerator that can be implemented on an FPGA. Then, we used Vivado tool to design the IP block and implement it on the ZYNQ ZCU106 FPGA. Finally, the video was recorded and H.264 compressed with Python code in the PYNQ framework, and the video encryption and decryption were accelerated using Crystals-Kyber hardware accelerator implemented on the FPGA.

A Guideline for the Location of Bus Stop Type considering the Interval Distance of Bus Stops and Crosswalks at Mid-Block (Mid-Block상의 버스정류장과 횡단보도 이격거리를 고려한 버스정류장 배치형태 기준 연구)

  • Lee, Su-Beom;Gang, Tae-Uk;Gang, Dong-Su;Kim, Jang-Uk
    • Journal of Korean Society of Transportation
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    • v.28 no.2
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    • pp.123-133
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    • 2010
  • The national standards for the installation of pedestrian crosswalks prohibits installation of crosswalks within 200 meters of nearby overpasses, underpasses, or crosswalks. In case the exceptional installation is required, the feasibility study is to be thoroughly conducted by the local police agency. However, it is an undeniable fact that the specific installation standards for optimal types and locations of crosswalks are not yet to be established. This paper examines the development of traffic accident prediction model applicable to different types and locations of bus stops(type A and type B) at mid-block intersections. Furthermore, it develops the poisson regression model which sets the "number of traffic accidents" and "traffic accident severity" as dependent variables, while using "traffic volumes", "pedestrian traffic volumes" and "the distance between crosswalks and bus stops" as independent variables. According to the traffic accident prediction model applicable to the type A bus stop location, the traffic accident severity increases relative to the number of traffic volumes, the number of pedestrian traffic volumes, and the distance between crosswalks and bus stops. In case of the type B bus stop model, the further the bus stop is from crosswalks, the number of traffic accidents decreases while it increases when traffic volumes and pedestrian traffic volumes increase. Therefore, it is reasonable to state that the bus stop design which minimizes the traffic accidents is the type C design, which is the one in combination of type A and type B, and the optimal distance is found to be 65 meters. In case of the type A design and the type B design, the optimal distances are found to be within range 60~70meters.

A Design of a Tile-Based Rasterizer Using Varying Interpolator by Pixel Block Unit (Pixel Block 단위 Varying Interpolator를 적용한 타일기반 Rasterizer 설계)

  • Kim, Chi-Yong
    • Journal of IKEEE
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    • v.18 no.3
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    • pp.403-408
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    • 2014
  • In this paper, we propose a rasterizer architecture using varying interpolator which process several pixels at a time. Proposed rasterizer is able to handle 16 pixel at a time and output the color of up to 64. It can reduce the redundancy of calculation by configuring a matrix transformation and matrix calculation for rasterization, and it can enhance the speed of rasterizer by increasing the reusability. As a result, proposed rasterizer has improve 11% in color interpolation, 17% in the processing speed of the rasterizer by comparing with conventional research.

A Study on Traction System Characteristics of High-Speed Train

  • Han, Young-Jae;Kim, Ki-Hwan;Seo, Sung-Il;Park, Chan-Kyoung;Han, Seong-Ho;Kim, Jong-Young;Kno, Ae-Sook
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1724-1726
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    • 2003
  • Korean High-Speed Train (350km/h), composed of 2 power cars, 2 motorized car and 3 trailer cars, has been developed and is under trial test. To verify the design requirements for the functions and traction performances of the train, KRRI (Korea Railroad Research Institute) decided to evaluate traction performances of the train during trial test. For this purpose, torque, velocity, voltage and current must be measured. KRRI has developed a measurement system that can measure vast and various signals effectively. In this paper, we introduce traction performances of Korean High-Speed Train. The traction measurement items are focused on the verification of motor block performances. Motor block consists of 2 motors. By this test, we verified traction performances of Korean High-Speed Train.

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Optimized Multiple Description Lattice Vector Quantization Coding for 3D Depth Image

  • Zhang, Huiwen;Bai, Huihui;Liu, Meiqin;Zhao, Yao
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.9 no.3
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    • pp.1140-1154
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    • 2015
  • Multiple Description (MD) coding is a promising alternative for the robust transmission of information over error-prone channels. Lattice vector quantization (LVQ) is a significant version of MD techniques to design an MD image coder. However, different from the traditional 2D texture image, the 3D depth image has its own special characteristics, which should be taken into account for efficient compression. In this paper, an optimized MDLVQ scheme is proposed in view of the characteristics of 3D depth image. First, due to the sparsity of depth image, the image blocks can be classified into edge blocks and smooth blocks, which are encoded by different modes. Furthermore, according to the boundary contents in edge blocks, the step size of LVQ can be regulated adaptively for each block. Experimental results validate the effectiveness of the proposed scheme, which show better rate distortion performance compared with the conventional MDLVQ.

A Study on the Designing for Rural Housing Block Considering Sustainable Development (지속가능한 개발을 위한 농촌전원단지 설계 연구)

  • Ryu, Soo-Hoon;Lee, Ho-Jung
    • Journal of The Korean Digital Architecture Interior Association
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    • v.8 no.2
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    • pp.83-92
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    • 2008
  • This study is about architectural design for rural housing block redevelopment for districts with existing residents considering sustainable development. The study suggests development direction focusing on preserving the regional characteristics, and presentation of suburban-style housing complex reflecting on the future tenant's individuality and demand. The preexisting development approach for suburban-style housing complex which was planned by the developer, failed to recognize taste of the future tenants. Profitability being the priority, it also resulted in a serious environmental disruption. In this development however, through a systematic direction for site development and site analysis, conducting surveys through future tenants, attempted for a continuous growth of the community. The study is presented covering the following areas; site's pathway system, nature conservation plan, lot plan, land use, arrangement plan, housing plan and community facility.

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Design of wide Band Microwave Amplifier with Good Frequncy Characteristics (주파수 특성이 좋은 광대역 마이크로웨이브 증폭기의 설계)

  • Kang, Hee-Chang;park, Il;Chin, Youn-kang
    • The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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    • v.2 no.2
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    • pp.3-10
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    • 1991
  • The new structure method of GaAs microwave amplifiers using DC block function and impedance transforming property of DC block/transformer(non-symmetrical two - microstrip coupled line and interdigital three - microstrip coupled line), instead of chip capacitor, is presented. The newly structured microwave amplifier showed wideband characteristics(bandwidth, 3.5 GHz) and flat frequency response. Interdigital three - microstrip coupled line which is used for microwave amplifier can be used to match amplifiers as well as DC blocking.

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Objective Picture Quality Assessment of Block Based Moving Picture Coder (블록기반 동영상 부호화기의 객관적 화질평가)

  • Chung, Tae-Yun;Hong, Min-Suk;Park, Kang-Seo;Kim, Hyun-Sool;Park, Sang-Hui
    • The Transactions of the Korean Institute of Electrical Engineers A
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    • v.48 no.12
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    • pp.1589-1598
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    • 1999
  • Conventional MSE or PSNR based methods for objective picture quality assessment of moving picture coder are not well correlated with subjective human evaluation. In recent years, the design of better objective quality assessment has attracted much intention and several picture quality metrics based on the properties of Human Visual System has been proposed. This paper proposes new metric which is appropriate for objective picture quality assessment of block based moving picture coder by considering frequency sensitivity, inter-intra channel masking and several distortion artifacts caused by block based coding. The experimental results show that the proposed method is good correlated with subjective assessment.

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A Design of RS Decoder for MB-OFDM UWB (MB-OFDM UWB 를 위한 RS 복호기 설계)

  • Choi, Sung-Woo;Shin, Cheol-Ho;Choi, Sang-Sung
    • Proceedings of the Korea Electromagnetic Engineering Society Conference
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    • 2005.11a
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    • pp.131-136
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    • 2005
  • UWB is the most spotlighted wireless technology that transmits data at very high rates using low power over a wide spectrum of frequency band. UWB technology makes it possible to transmit data at rate over 100Mbps within 10 meters. To preserve important header information, MB-OFDM UWB adopts Reed-Solomon(23,17) code. In receiver, RS decoder needs high speed and low latency using efficient hardware. In this paper, we suggest the architecture of RS decoder for MB-OFDM UWB. We adopts Modified-Euclidean algorithm for key equation solver block which is most complex in area. We suggest pipelined processing cell for this block and show the detailed architecture of syndrome, Chien search and Forney algorithm block. At last, we show the hardware implementation results of RS decoder for ASIC implementation.

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Design of Inner Key scheduler block for Smart Card (스마트 카드용 내장형 키 스케쥴러 블록 설계)

  • Song, Je-Ho
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.11 no.12
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    • pp.4962-4967
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    • 2010
  • Security of the electronic commercial transaction especially through the information communication network is gaining its significance due to rapid development of information and communication related fields. For that, some kind of cryptographic algorithm is already in use for the smart card. However, the growing needs of handling multimedia and real time communication bring the smart card into more stringent use of its resources. Therefore, we proposed a key scheduler block of the smart card to facilitate multimedia communication and real time communication.