• 제목/요약/키워드: block design

검색결과 3,009건 처리시간 0.034초

모토롤라 MPC8XX 마이크로프로세서와 데이터 저장장치간 고속 데이터 입/출력부 설계 및 구현 (Design and Implementation of High Speed Data I/O Block Between Motorola MPC8XX Microprocessor and Memory Devices)

  • 김기홍;이승수;황인호
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2003년도 하계종합학술대회 논문집 V
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    • pp.2637-2640
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    • 2003
  • In this paper, we propose a simple and efficient data input/output block with high speed between Motorola MPC8XX microprocessor and memory devices. Proposed method is capable of high speed data read and write using the address decoder and the burst cycle between Motorola PowerPC based MPC8XX microprocessor and fixed address locating memory devices such as FIFO, PCMCIA card, and so on. Experimental results are given our findings and discussions.

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CMOS Second Generation Current Conveyor의 설계 (The Design of CMOS Second Generation Current Conveyor)

  • 오재환;김상수이영훈
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1998년도 추계종합학술대회 논문집
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    • pp.1037-1040
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    • 1998
  • In this paper, current conveyor building block is introduced and CMOS realization of this block is given. The input-impedance characteristics, current-transfer characteristics and voltage-transfer characteristics of this proposed current conveyor circuit are given. This characteristics of the CMOS current conveyor circuit is useful of the various applications which require a wideband. Using the Spice tool, the circuit is designed and the characteristics of CMOS current conveyor circuit is considered. Finally, refer to the simple applications.

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혼합물실험(混合物實驗)의 공정변수(工程變數)에 관한 교락(交絡) block 효과(效果) (Block Confounding Effect for Mixture Experiments with Process Variables)

  • 정중희;김정만
    • 품질경영학회지
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    • 제13권2호
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    • pp.66-72
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    • 1985
  • The objective of mixture experiments with process variables is to find experimental blends and conditions that produce the product of highest quality. In this paper, designs for mixture experiments with process variables are presented, where the emphasis is on using only a fraction of the total number of possible design points and the fitting of reduced models for measuring the effects of the mixture components and process variables.

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APPLICATION OF $(\upsilon,\kappa,\lambda)$-CONFIGURATION TO GENERATION OF A CONFERENCE KEY

  • Chung, Il-Yong
    • Journal of applied mathematics & informatics
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    • 제8권2호
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    • pp.531-537
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    • 2001
  • In order for all participants at video conference to communicate mutually, the conference key should be necessary. In this paper, we present the communication protocol that generates a conference key efficiently based on $(\upsilon,\kappa,\lambda)$-configuration, one class of block designs, which minimizes message transmission overhead needed for this key. Especially, in the case of ${\lambda}=1$, the protocol requires only $O(\sqrt[v]{v})$ messages, where v is the number of participants.

An Optimal Scheme of Inclusion Probability Proportional to Size Sampling

  • Kim Sun Woong
    • Communications for Statistical Applications and Methods
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    • 제12권1호
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    • pp.181-189
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    • 2005
  • This paper suggest a method of inclusion probability proportional to size sampling that provides a non-negative and stable variance estimator. The sampling procedure is quite simple and flexible since a sampling design is easily obtained using mathematical programming. This scheme appears to be preferable to Nigam, Kumar and Gupta's (1984) method which uses a balanced incomplete block designs. A comparison is made with their method through an example in the literature.

분리최적화 기법을 이용한 강인제어기 설계 (Robust compensator design for parametric uncertain systems by separated optimizations)

  • 김경수;박영진
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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    • pp.589-592
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    • 1996
  • It is well known that robust compensators designed by the block-diagonal Lyapunov function approaches are conservative while they are popular in practice because of their computational easiness. In this note, we develop a systematized version of conventional block-diagonal Lyapunov function approaches by deriving two separated optimizations based on the guaranteed cost control method. The proposed method generates reasonable robust compensators in practice.

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비트 플레인을 이용한 움직임 추정기 설계의 관한 연구 (A Study on Motion Estimator Design Using Bit Plane)

  • 김병철;조원경
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 하계종합학술대회 논문집
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    • pp.403-406
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    • 1999
  • Among the compression methods of moving picture information, a motion estimation method is used to remove time-repeating. The Block Matching Algorithm in motion estimation methods is the commonest one. In recent days, it is required the more advanced high quality in many image processing fields, for example HDTV, etc. Therefore, we have to accomplish not by means of Partial Search Algorithm, but by means of Full Search Algorithm in Block Matching Algorithm. In this paper, it is suggested a structure that reduce total calculation quantity and size, because the structure using Bit Plane select and use only 3bit of 8bit luminance signal.

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2인자 혼합모형의 제약과 비제약 설계에 의한 게이지 R&R 연구의 고찰 (Review of Gauge R&R Studies by Restricted and Unrestricted Design in the Two-Factor Mixed Model)

  • 최성운
    • 대한안전경영과학회:학술대회논문집
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    • 대한안전경영과학회 2009년도 추계학술대회
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    • pp.657-665
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    • 2009
  • The paper reviews gauge R&R studies by two-factor mixed models including random and fixed factors. The two-factor mixed models include restricted models and unrestricted models considering the interaction of two factors. This study also classifies the models according to the number of factors, and the combination of various factors such as random factor, fixed factor, block factor and repetition type.

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MP@ML Half-pel을 지원하는 고성능 완전 탐색 움직임 추정기 VLSI 설계 (Design of High Performance full search Motion Estimation VLSI with Half-pel)

  • 최홍규;남승현;이문기
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(4)
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    • pp.287-290
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    • 2002
  • The block matching algorithm motion estimation is a soft-core for hardwired motion estimation block in MPEG-2, H.261 encoder. This motion estimation has been tested and verified to be valid for implementation of FPGA. Efficiency performance of the synthesized motion estimation was up to 89%, and the average PSNR between the original image and the motion-compensated image is 38dB.

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차분 전력 분석에 안전한 역원기의 설계 (DPA-Resistant Design of the Inverter)

  • 김희석;조영인;한동국;홍석희
    • 한국정보통신설비학회:학술대회논문집
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    • 한국정보통신설비학회 2008년도 정보통신설비 학술대회
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    • pp.340-344
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    • 2008
  • In the block cipher, DPA-resistant masking methods make an appropriation of extremely high cost for the non-linear part. Block ciphers like AES and ARIA use the inversion operation as this non-linear part. This make various countermeasures be proposed for reducing the cost of masking inversion. In this paper, we propose the efficient masking inverter by rearranging the masking inversion operation over the composite field and finding duplicated multiplications.

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