• Title/Summary/Keyword: block codes

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Low Density Codes Construction using Jacket Matrices (잰킷 행렬을 이용한 저밀도 부호의 구성)

  • Moon Myung-Ryong;Jia Hou;Hwang Gi-Yean;Lee Moon-Ho;Lee Kwang-Jae
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.8 s.338
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    • pp.1-10
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    • 2005
  • In this paper, the explicit low density codes construction from the generalized permutation matrices related to algebra theory is investigated, and we design several Jacket inverse block matrices on the recursive formula and permutation matrices. The results show that the proposed scheme is a simple and fast way to obtain the low density codes, and we also Proved that the structured low density parity check (LDPC) codes, such as the $\pi-rotation$ LDPC codes are the low density Jacket inverse block matrices too.

Nonbinary Multiple Rate QC-LDPC Codes with Fixed Information or Block Bit Length

  • Liu, Lei;Zhou, Wuyang;Zhou, Shengli
    • Journal of Communications and Networks
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    • v.14 no.4
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    • pp.429-433
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    • 2012
  • In this paper, we consider nonbinary quasi-cyclic low-density parity-check (QC-LDPC) codes and propose a method to design multiple rate codes with either fixed information bit length or block bit length, tailored to different scenarios in wireless applications. We show that the proposed codes achieve good performance over a broad range of code rates.

AN ALTERED GROUP RING CONSTRUCTION OF THE [24, 12, 8] AND [48, 24, 12] TYPE II LINEAR BLOCK CODE

  • Shefali Gupta;Dinesh Udar
    • Bulletin of the Korean Mathematical Society
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    • v.60 no.3
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    • pp.829-844
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    • 2023
  • In this paper, we present a new construction for self-dual codes that uses the concept of double bordered construction, group rings, and reverse circulant matrices. Using groups of orders 2, 3, 4, and 5, and by applying the construction over the binary field and the ring F2 + uF2, we obtain extremal binary self-dual codes of various lengths: 12, 16, 20, 24, 32, 40, and 48. In particular, we show the significance of this new construction by constructing the unique Extended Binary Golay Code [24, 12, 8] and the unique Extended Quadratic Residue [48, 24, 12] Type II linear block code. Moreover, we strengthen the existing relationship between units and non-units with the self-dual codes presented in [10] by limiting the conditions given in the corollary. Additionally, we establish a relationship between idempotent and self-dual codes, which is done for the first time in the literature.

Nominal flexural strength of high-strength concrete beams

  • Al-Kamal, Mustafa Kamal
    • Advances in concrete construction
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    • v.7 no.1
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    • pp.1-9
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    • 2019
  • The conventional ACI rectangular stress block is developed on the basis of normal-strength concrete column tests and it is still being used for the design of high-strength concrete members. Many research papers found in the literature indicate that the nominal strength of high-strength concrete members appears to be over-predicted by the ACI rectangular stress block. This is especially true for HSC columns. The general shape of the stress-strain curve of high-strength concrete becomes more likely as a triangle. A triangular stress block is, therefore, introduced in this paper. The proposed stress block is verified using a database which consists of 52 tested singly reinforced high-strength concrete beams having concrete strength above 55 MPa (8,000 psi). In addition, the proposed model is compared with models of various design codes and proposals of researchers found in the literature. The nominal flexural strengths computed using the proposed stress block are in a good agreement with the tested data as well as with that obtained from design codes models and proposals of researchers.

A Versatile Reed-Solomon Decoder for Continuous Decoding of Variable Block-Length Codewords (가변 블록 길이 부호어의 연속 복호를 위한 가변형 Reed-Solomon 복호기)

  • 송문규;공민한
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.3
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    • pp.187-187
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    • 2004
  • In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

A Versatile Reed-Solomon Decoder for Continuous Decoding of Variable Block-Length Codewords (가변 블록 길이 부호어의 연속 복호를 위한 가변형 Reed-Solomon 복호기)

  • 송문규;공민한
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.41 no.3
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    • pp.29-38
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    • 2004
  • In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

Efficient Parallel Block-layered Nonbinary Quasi-cyclic Low-density Parity-check Decoding on a GPU

  • Thi, Huyen Pham;Lee, Hanho
    • IEIE Transactions on Smart Processing and Computing
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    • v.6 no.3
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    • pp.210-219
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    • 2017
  • This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

Quasi-Orthogonal Space-Time Block Codes Designs Based on Jacket Transform

  • Song, Wei;Lee, Moon-Ho;Matalgah, Mustafa M.;Guo, Ying
    • Journal of Communications and Networks
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    • v.12 no.3
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    • pp.240-245
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    • 2010
  • Jacket matrices, motivated by the complex Hadamard matrix, have played important roles in signal processing, communications, image compression, cryptography, etc. In this paper, we suggest a novel approach to design a simple class of space-time block codes (STBCs) to reduce its peak-to-average power ratio. The proposed code provides coding gain due to the characteristics of the complex Hadamard matrix, which is a special case of Jacket matrices. Also, it can achieve full rate and full diversity with the simple decoding. Simulations show the good performance of the proposed codes in terms of symbol error rate. For generality, a kind of quasi-orthogonal STBC may be similarly designed with the improved performance.

Design of the layered coding with rate compatible block turbo codes (블록 터보 부호를 이용한 계층적 부호화 방식 설계)

  • Oh, Ji-Won;Hwang, Ki-Seon;Lee, Jing;Kim, Soo-Young
    • Proceedings of the IEEK Conference
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    • 2007.07a
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    • pp.87-88
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    • 2007
  • In this paper, we propose a design of the layered coding with block turbo codes. The proposed scheme can be used efficiently for multimedia broadcasting and multicasting services by adaptive selection of a modulation and coding scheme at a receiver. This paper demonstrates various design examples of the layered coding using rate compatible block turbo codes.

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A Study on the Legislation Types and Prescriptions of American Earth Building Codes (미국 흙건축 법규의 법제화 유형 및 규제내용 분석)

  • Kim, Jeong-Gyu
    • KIEAE Journal
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    • v.8 no.3
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    • pp.19-26
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    • 2008
  • The purpose of this study is to analyze the legislation types and prescriptions of American earth building codes. The process of this study is as follows: (1) To understand the legislation background of American earth building codes, this study investigated the history and present state of earth building techniques which is used in USA. (2) To understand the legislation method and procedure of American earth building codes, this study investigated the legislation system of American building codes and the process of model building codes development and adoption. (3) To provide basic data for the legislation of Korean earth building codes or guidelines, this study analyzed American earth building codes about adobe, compressed earth block and rammed earth. The result of this study is as follows: (1) To meet need of a single coordinated set of national model building codes in the United States, the nation's three model code groups decided to form the International Code Council and the first edition of the International Building Code was published in 1997. In the International Building Code there are prescriptions on adobe construction. (2) There are three legislation types of earth building codes in USA. First is to use prescriptions of International Building Code on adobe construction. Second is that State governments establish and issue a separate document under its own title. The last is that local jurisdictions adopt International Building Code with amendments or additional rules. (3) On the base of analysis of American earth building codes, this study proposed the legislation process and direction of Korean earth building codes and guidelines.