• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1562-1574
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• 1998

We, in this paper, have implemented T1, E1 and fractional E1 HDSL(High-bit-rate digital subscriber line) function over an ATM switching system. The maxi$\mu$ loop lengths for subscriber service and cell loss rates to meet the bit error rate of 10$^{-7}$ at transmission of 2B1Q HDSL data E1 rate over existing telephone copper wires in the presence of the significant impairments such as NEXT(Nearned crosstalk), impulse noise, power line noise and longitudinal over the CSAs environment consisting of 26 gauge and 25 gauge unloaded copper telephone lines has assessed. HDSL will intially be used to serve private-DS1, ISDN-BRA, and DLC feeders, later DS1 extension from optic fiber cable. We also present market provision for the HDSL.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.193-198
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• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.26-27
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• 2006

To develop tera-bit level SONOS flash memories, SONOS unit memory and 64 bit flash arrays are fabricated. The unit cells have both channel length and width of 30nm. The NAND & NOR arrays are fabricated on SOI wafer and patterned by E-beam. The unit cells represent good write/erase characteristics and reliability characteristics. SSL-NOR array have normal write/erase operation. These researches are leading the realization of Tera-bit level non-volatile nano flash memory.

• ETRI Journal
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• v.26 no.6
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• pp.520-534
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• 2004

As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.

• Transactions on Electrical and Electronic Materials
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• v.11 no.5
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• pp.238-241
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• 2010

The purpose of this study is to solve the problems of radio frequency bandwidth frequency depletion, confusion possibilities, and security that are in current wireless communications systems, and to confirm the possibility of applying those solutions for the next generation network. To solve the problems of the current wireless communications system, a visible light communications system for power line communication (PLC) via 8-bit microcontroller is created and the capacity is analyzed. The exclusive PLC chip APLC-485MA, an 8-bit ATmega16 microcontroller, high brightness 5pi light emitting diodes (LEDs), and the LLS08-A1 visible light-receiving sensor were used for the transmitter and receiver. The performance was analyzed using a designed program and an oscilloscope. The voltage change was measured as a function of distance from 10-50 cm. Blue LEDs showed the best performance among the measured LED types, with 0.47 V of voltage loss, but for a distance over 50 cm, precise data was not easy to obtain due to the weak light. To overcome these types of problems, specific values such as the changing conditions and efficiency value relevant to the light emitting parts and the visible light-receiving sensor should be calculated, and continuous study and improvements should also be realized for better communication conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.347-356
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• 1987

This paper is to propose a new line code suitable for a high speed unipolar pulse transmission system, such as a high speed optical digital transmission system. The original information speed can be converted into the transmission speed $\frac{(m+1)}{m}$ by the speed converter. Then this code, named mBiZ code, is generated by means of an Exclusive NOR between the bit stream inserted a space into every m bits and the bit stream delayed by the time slot allocated a single bit at the output coded sequence. Therefore, a mBiZ code can reduce a redundancy in the line code for transmission and its conversion circuits can be devised easily. The mBiZ code can also suppress undesirable long consecuitive identical digits and make line code balance in the mark and space ratio. Therefore, high frequency and low frequency components in power spectrum of a mBiZ code can be suppessed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.43-47
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• 2021

This paper investigates the network throughput of PLC (Power Line Communication) system in the in-building network. The OFDM (Orthogonal Frequency Division Multiplexing) modulation format and adaptive bit loading algorithm is used to minimize the effect of signal loss and noise on transmission performance in the power line channel characterized by frequency selective fading. The network throughput of the PLC system which consists of gateway and CPE（Customer Premise Equipment) PLC modem in the in-building network is measured by network performance measurement tool, iperf and analyzed according to the TCP (Transmission Control Protocol) window size.

• Journal of Electrical Engineering and information Science
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• v.3 no.3
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• pp.300-305
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• 1998

This paper describes new sense amplifier with fast sensing delay time of 0.54ns and 32kb CMOS embedded SRAM with 4.67 ns access time for a 3-V power supply. It was achieved using the sense amplifier with multiple point sensing scheme and highs peed bit-line scheme. The sense amplifier saves 25% of the power dissipation compared with the conventional one while maintaining a very short sensing delay. The SRAM uses 0.5m double-polysilicon and triple-metal CMOS process technology. A die size is 1.78${\times}$mm2.13mm.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.797-800
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• 2005

In this paper, the designed 10-bit current steering data driving circuit consists of bias circuits, shift registers, data and line latches, level shifters, and 10-bit D/A converters. This data driving circuit can improve image quality, driving speed, and can reduce process error, DNL error, and glitch noise. To reduce current cells, the 10-bit D/A converter was designed 3+3+4 hybrid type. As a result 49 current cells are decreased. The transient analysis shows that currents flows a few of mA in data line and the currents have 1024 gray levels of current values. Total circuits are designed for 10 ${\mu}s$ speed. Thus the designed 10-bit current steering data driving circuit can be usable in HDTV/XGA AMOLED displays. These data driving circuits are designed for 0.35 ${\mu}m$ CMOS process at 3.3 V and 18 V supply voltage and simulated with HSPICE..

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6C
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• pp.569-574
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• 2006

We derive the general power spectral density of functions of ultra-wide bandwidth (UWB) systems using a pulse position modulation. We propose a new UWB system with a preferable line spectrum properies and a good bit error rate performance.