• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.902-905
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• 2004

A heart diagnosis system adopts Superconducting Quantum Interface Device(SQUID) sensors for precision MCG signal acquisitions. Such system is composed of hundreds of sensors, requiring fast signal sampling and precise analog-digital conversions(ADC). Our development of hardware board, processing 64-channel 12-bit 1ks/s, is built by using 8-channel ADC chips, 8-bit microprocessors, SPI interfaces, and parallel data transfers between microprocessors to meet the 1ks/s, i.e. 1 ms speed. The test result shows that the signal acquisition is done in 168 usuc which is much shorter than the required 1 ms period. This hardware will be extended to 256 channel data acquisition to be used for the diagnosis system.

• Journal of Korea Society of Industrial Information Systems
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• v.17 no.5
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• pp.37-42
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• 2012

Audio steganography is quite similar to the procedure of modifying the least significant bit(LSB) of image media files. The most widely used technique today is hiding of secret messages into a digitized audio signal. In this paper, I propose a new method for hiding messages from attackers, high data inserting rate is achieved. In other words, based on the LSB hiding method and digitized to change the bit position of a secret message, an encrypted stego medium sent to the destination in safe way.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.327-330
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• 2008

This paper shows an implementation of WLAN-based Audio/Video(A/V) system for multimedia home networks. Proposed WLAN-based A/V system can transmit multimedia data of high quality. The entire system consists of a 16-bit RISC controller, a program ROM, a SRAM, timers, an interrupt controller, a DART, GPIOs, an I2C and the OFDM modem supporting for the IEEE 802.11g standard. The simple MAC functions are implemented by firmware on an embedded 16-bit RISC controller. The OFDM modem supports a complete set of data rates up to 54Mbps. Proposed the system is implemented by an Altera FPGA EP1S60F1020C6 device, a 10-bit 2-ch DAC, a 10-bit 2-ch ADC and RF/IF chips.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.401-404
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• 2010

In multibit Sigma-Delta Modulator, DWA(Data Weighted Averaging) among the DEM(Dynamic Element Matching) techniques was widely used to get rid of non-linearity that caused by mismatching of unit capacitor in feedback DAC path. this paper proposed the improved DWA architecture by adjusting clock timing of the existing DWA architecture. 2n Register block used for output was replaced with 2n S-R latch block. As a result of this, MOS Tr. can be reduced and extra clock can also be removed. Moreover, two n-bit Register block used to delay n-bit data code is decreased to one n-bit Register. In order to confirm characteristics, DWA for the 3-bit output with the proposed DWA architecture was designed on 0.18um process under 1.8V supply. Compared with the existing architecture. It was able to reduce the number of 222 MOS Tr.

• The Pure and Applied Mathematics
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• v.11 no.1
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• pp.1-14
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• 2004

Due to the development of computer network and mobile communications, the security in image data and other related source are very important as in saving or transferring the commercial documents, medical data, and every private picture. Nonetheless, the conventional encryption algorithms are usually focusing on the word message. These methods are too complicated or complex in the respect of image data because they have much more amounts of information to represent. In this sense, we proposed an efficient secret symmetric stream type encryption algorithm which is based on Boolean matrix operation and the characteristic of image data.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.59-70
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• 1993

An efficient test method based on march test is presented to cover line leakage failures associated with bit and word lines or mega bit DRAM chips. A modified column march (Y-march) pattern is derived to improve fault coverage against the data retention failure. Time delay concept is introduced to develop a new column march test algorithm detecting various data retention failures. A built-in test circuit based on the column march pattern is designed and verified using logic simulation, confirming correct test operations.

• Journal of the Korea Computer Graphics Society
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• v.24 no.1
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• pp.27-33
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• 2018

This paper presents a new adaptive LSB steganography for high capacity in spatial color images. The number of least signi ficant bit (LSB) of each RGB component in a color image pixel, to replace with the data bits to be hidden, was determine d through analysis of the worst case peak signal noise ratio (PSNR). In addition, the combination of the number of bits is determined adaptively according to image content. That is, 70% of the data to be hidden is proposed to be replaced with 3 bit LSB of two components, 2 bit LSB of the rest component, and 30% be replaced with 4 bit LSB of each RGB compon ent. To find edge areas in an image, delta sorting in local area is also suggested. Using the proposed method, the data cap acity is 9.2 bits per pixel (bpp). The average PSNR value of the tested images with concealed data of up to 60Kbyte was 43.9 db and also natural histograms were generated.