• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.815-818
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• 2003

New sensing and writing schemes for a magneto-resistive random access memory (MRAM) with a twin cell structure are proposed. In order to enhance the cell reliability, a scheme of the low voltage precharge is employed to keep the magneto resistance (MR) ratio constant. Moreover, a common gate amplifier is utilized to provide sufficient voltage signal to the bit line sense amplifiers under the small MR ratio structures. To enhance the writing reliability, a current mode technique with tri-state current drivers is adopted. During write operations, the bit and /bit lines are connected. And 'HIGH' or 'LOW' data is determined in terms of the current direction flowing through the MTJ cell. With the viewpoint of the improved reliability of the cell behavior and sensing margin, HSPICE simulations proved the validity of the proposed schemes.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.481-484
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• 2003

OFDM(Orthogonall Frequency Division Multiplexing) is an efficient transmission techniques for the frequency selective fading wireless channel where conventional modulations suffer from severe performance degradation. Recently, more efficient techniques for the OFDM are paid much attention such as adaptive modulation for each subcarrier, since more bit rate has been required for the wireless data network [1-3]. The proposed system employs the adaptive modulation between transmitter and receiver in each subcarrier, where the bit and power is properly allocated. Also multiple antenna system called MIMO is considered, which result in robustness in channel delay, improved power efficiency and improved bit SNR for the given BER.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.235-238
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• 2002

This paper proposes a novel scheme of designating non-cacheable addresses of memories in embedded systems of multi-master architectures without a Memory Management Unit (MMU). As a solution for data coherency problem between external memories and a cache memory, we proposes a cache masking scheme by allocating the most significant bit of address not used in 32-bit address system as indicator bit to designate non-cacheable address. As this scheme enables non-cacheable area designation every address, the simpler in the aspect of hardware and more flexible size of non-cacheable area can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.252-256
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• 2006

A low-power ECC check bit generator is presented with competent DRAM implementation with minimal speed loss, area overhead and power consumption. The ECC used in the proposed scheme is a variant form of the minimum weight column code. The spatial and temporal correlations of input data are analyzed and the input paths of the check bit generator are ordered for the on-line adaptable power savings up to 24.4% in the benchmarked cases. The chip size overhead is estimated to be under 0.3% for a 80nm 1Gb DRAM implementation.

• Journal of the Korean Mathematical Society
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• v.50 no.4
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• pp.879-897
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• 2013

Shannon entropy is one of the widely used randomness measures especially for cryptographic applications. However, the conventional entropy tests are less sensitive to the inter-bit dependency in random samples. In this paper, we propose new online randomness test schemes for true random number generators (TRNGs) based on the mutual information between consecutive ${\kappa}$-bit output blocks for testing of inter-bit dependency in random samples. By estimating the block entropies of distinct lengths at the same time, it is possible to measure the mutual information, which is closely related to the amount of the statistical dependency between two consecutive data blocks. In addition, we propose a new estimation method for entropies, which accumulates intermediate values of the number of frequencies. The proposed method can estimate entropy with less samples than Maurer-Coron type entropy test can. By numerical simulations, it is shown that the new proposed scheme can be used as a reliable online entropy estimator for TRNGs used by cryptographic modules.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.1
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• pp.162-172
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• 1997

In this paper, we investigated the performance of a binary feedback switch algorithm for the ABR(Available Bit Rate) service in ATM networks. A binary feedback switch is also called EFCI(Explicit Forward Congestion Indication) switch and can be classificed into input cell processing(IP) scheme according to processing methods for the EFCI bit in data-cell header. We proposed two implementation methods for the binary feedback switch according to EFCI-bit processing schemes, and analyzed the ACR(Allowed Cell Rate) of source and the queue length of switch for each scheme in steady state. In addition, we derived the upper and lower bounds for maximum and minimum queue lengths, respectively, and investigated the impact of ABR parameters on the queue length.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.671-672
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• 2006

Recently Communication with using IrDA is bing used in various fields. In this paper I designed a receiver by fabricating hardware that used to be fabricated through software, so anyone who don't have knowledge on IrDA can receive Ir Signal easily. This receiver can communicate with CPU through 8 bit data and 3 bit address. Also this receiver can use user-needed CLK because this receiver embodied 16 bit CLK Prescaler.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.893-894
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• 2006

DSP based on a 8 bit microprocessor was studied for ECG and PPG signals. Digital filtering has an advantage of reducing hardware components in system-on-chip design. However, low resolution such as in 8 bit data has much difficulties in DSP. We demonstrated a comparable performance of DSP filtering compared with analog filters.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.841-842
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• 2006

This paper has proposed a serial 8-bit DAC for column driver circuits of mobile displays using LTPS TFTs. The DAC circuit takes very small area by using parasitic capacitance of column lines as sampling and holding capacitors. Moreover, the proposed DAC does not need the analog buffer, because the DAC operation is performed on the column lines. For the data driver circuits of 2-inch qVGA OLED panel, the DAC area is $84um{\times}800um$ and the simulated DAC power consumption is 8.5mW with 10-V supply voltage.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.