• 제목/요약/키워드: bipolar process

검색결과 231건 처리시간 0.025초

레오로지 박판의 전자교반을 응용한 진공 저압주조 제조공정 (Fabrication Process of Rheology Material Thin Plate Using Vacuum Low Pressure Die-casting Process with Electromagnetic Stirring)

  • 장신규;배정운;진철규;강충길
    • 한국주조공학회지
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    • 제32권1호
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    • pp.16-23
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    • 2012
  • In this study, we develop the lower pressure die casting with rheo-forming process of A356 aluminum alloy and vacuum system which can control the crystal size and obtain the high strengthened-light material. Using this process, we fabricate the thin plate for bipolar plate through the low pressure die casting with electromagnetic stirring and vacuum-evacuation which can control the crystal grain by electromagnetic stirring. Thin plate ($110mm{\times}130mm{\times}1mm$) is fabricated by this process. The average Vickers hardness of thin plate is about 77 HV.

실리콘-게르마늄 바이시모스 공정에서의 실리콘-게르마늄 이종접합 바이폴라 트랜지스터 열화 현상 (Degradation of the SiGe hetero-junction bipolar transistor in SiGe BiCMOS process)

  • 김상훈;이승윤;박찬우;강진영
    • 한국진공학회지
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    • 제14권1호
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    • pp.29-34
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    • 2005
  • 실리콘-게르마늄 바이시모스(SiGe BiCMOS) 소자 제작시 발생하는 실리콘-게르마늄 이종접합 바이폴라 트랜지스터(SiGe HBT) 열화 현상에 대하여 고찰하였다. 독립적으로 제작된 소자에 비해 SiGe BiCMOS 공정에서의 SiGe HBT소자는 얼리 전압(Early voltage), 콜렉터-에미터 항복전압 및 전류이득등의 DC특성이 열화되고 상당한 크기의 베이스 누설전류가 존재한다는 것을 알 수 있었다. 또한 AC 특성인 차단주파수(f/sub T/) 및 최대 진동주파수(f/sub max/)도 1/2이하로 현저하게 저하되는 것을 확인하였다. 이는 고온의 소오스-드레인 열처리에 의한 붕소의 농도분포 변화가 에미터-베이스 및 콜렉터-베이스 접합 위치에 변화를 주고, 결국 실리콘-게르마늄 내에서의 접합 형성이 이루어지지 않아 전류 이득이 감소하고 기생 장벽이 형성되어서 발생한 현상이다.

비-휘발성 저항 변화 메모리 응용을 위한 WOx 물질의 전기적 특성 연구 (A Study of the Electrical Characteristics of WOx Material for Non-Volatile Resistive Random Access Memory)

  • 정균호;김경민;송승곤;박윤선;박경완;석중현
    • 한국전기전자재료학회논문지
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    • 제29권5호
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    • pp.268-273
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    • 2016
  • In this study, we observed current-voltage characteristics of the MIM (metal-insulator-metal) structure. The $WO_x$ material was used between metal electrodes as the oxide insulator. The structure of the $Al/WO_x/TiN$ shows bipolar resistive switching and the operating direction of the resistive switching is clockwise, which means set at negative voltage and reset at positive voltage. The set process from HRS (high resistance state) to LRS (low resistance state) occurred at -2.6V. The reset process from LRS to HRS occurred at 2.78V. The on/off current ratio was about 10 and resistive switching was performed for 5 cycles in the endurance characteristics. With consecutive switching cycles, the stable $V_{set}$ and $V_{reset}$ were observed. The electrical transport mechanism of the device was based on the migration of oxygen ions and the current-voltage curve is following (Ohm's Law ${\rightarrow}$ Trap-Controlled Space Charge Limited Current ${\rightarrow}$ Ohm's Law) process in the positive voltage region.

새로운 A급 바이폴라 $CCII{\pm}$와 이를 이용한 출력 전류 제어 가능한 CCII+ 설계 (A Design of Novel Class-A bipolar $CCII{\pm}$ and Its Application to output Current Controllable CCII+)

  • 차형우
    • 대한전자공학회논문지SD
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    • 제48권11호
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    • pp.48-56
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    • 2011
  • 전기적인 조정(tuning) 시스템에 사용하기 위해, 차동출력을 갖는 새로운 A급 $CCII{\pm}$와 이를 이용한 출력 전류 제어가능한 CCII+를 설계하였다. 설계한 $CCII{\pm}$는 종래의 CCII+와 상보적인 교차 전류원으로 구성된다. 또한, 출력 전류 제어가능한 CCII+는 제안한 $CCII{\pm}$와 단일 출력을 갖는 전류 이득 증폭기로 구성된다. 시뮬레이션 결과 $CCII{\pm}$$1.9{\Omega}$의 전류 입력단자의 임피던스와 우수한 전압 및 전류 폴로워 특성을 갖고 있다는 것을 확인하였다. 제안한 CCII+는 $100{\mu}A$에서 10mA의 바이어스 제어 전류 범위에서 10MHz의 3-dB 주파수을 갖고 있으며, 출력 전류 제어 범위는 4-디케이드(decade)이다. CCII+의 전력소비는 ${\pm}2.5V$ 공급전압에서 4.5mW이다.

인산형 연료전지 분리판용 천연흑연-불소수지계 복합재료의 흑연입도에 따른 전기비저항 변화 (Electrical Resistivity of Natural Graphite-Fluorine Resin Composite for Bipolar Plates of Phosphoric Acid Fuel Cell(PAFC) Depending on Graphite Particle Size)

  • 이상민;백운경;김태진;노재승
    • 한국재료학회지
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    • 제27권12호
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    • pp.664-671
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    • 2017
  • A composite material was prepared for the bipolar plates of phosphoric acid fuel cells(PAFC) by hot pressing a flake type natural graphite powder as a filler material and a fluorine resin as a binder. Average particle sizes of the powders were 610.3, 401.6, 99.5, and $37.7{\mu}m$. The density of the composite increased from 2.25 to $2.72g/cm^3$ as the graphite size increased from 37.7 to $610.3{\mu}m$. The anisotropy ratio of the composite increased from 1.8 to 490.9 as the graphite size increased. The flexural strength of the composite decreased from 15.60 to 8.94MPa as the graphite size increased. The porosity and the resistivity of the composite showed the same tendencies, and decreased as the graphite size increased. The lowest resistivity and porosity of the composite were $1.99{\times}10^{-3}{\Omega}cm$ and 2.02 %, respectively, when the graphite size was $401.6{\mu}m$. The flexural strength of the composite was 10.3MPa when the graphite size was $401.6{\mu}m$. The lowest resistance to electron mobility was well correlated with the composite with lowest porosity. It was possible the flaky large graphite particles survive after the hot pressing process.

고분자전해질 연료전지용 Ti 분리판을 위한 고분자와 Ti Sol-Gel 탄소코팅의 비교 연구 (Comparison Study of Polymer and Ti Sol-Gel Carbon Coating on Ti for PEMFC Bipolar Plates)

  • 양원석;이재호;노희석;유주현;박철민;이수연;문성모
    • Corrosion Science and Technology
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    • 제22권6호
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    • pp.447-456
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    • 2023
  • In this work, we performed a comparative study examining two coatings on Ti Gr.1 for use in fuel cell bipolar plates. The coatings consisted of carbon black as the conductor along with acrylic polymer and Ti Sol-Gel binder as the binder. Ti Sol-Gel that had precipitated as TiO2 in areas impregnated between carbon black gaps, thereby acting as a binder for carbon black and serving as a polymer coating. Neither of the coatings peeled off during the 90° bend test to check formability. The contact resistance of the TiO2 coating was found to be lower than that of the polymer binder coating. Moreover, due to coating shrinkage (denser) that occurred during the heat treatment process, the TiO2 binder coating showed almost the same level of corrosion resistance, as measured by potentiostatic and EIS tests, despite being thinner than the polymer coating. However, both the polymer binder coating and the TiO2 binder coating had many pores and irregularities internally (around 10 ~ 100 nm) and on the surface (0.1 ~ 2 ㎛). We considered that these pores and irregularities contributed to the lower corrosion resistance.

Temperature Stable Current Source Using Simple Self-Bias Circuit

  • Choi, Jin-Ho
    • Journal of information and communication convergence engineering
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    • 제7권2호
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    • pp.215-218
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    • 2009
  • In this paper, temperature stable current and voltage references using simple CMOS bias circuit are proposed. To obtain temperature stable characteristics of bias circuit a bandgap reference concept is used in a conventional circuit. The parasitic bipolar transistors or MOS transistors having different threshold voltage are required in a bandgap reference. Thereby the chip area increase or the extra CMOS process is required compared to a standard CMOS process. The proposed reference circuit can be integrated on a single chip by a standard CMOS process without the extra CMOS process. From the simulation results, the reference current variation is less than ${\pm}$0.44% over a temperature range from - $20^{\circ}C$ to $80^{\circ}C$. And the voltage variation is from - 0.02% to 0.1%.

Teletext Bit Slicer 집적회로의 설계 및 제작 (Design and Fabrication of Teletext Bit Slicer IC)

  • 申明澈;張榮旭;金永生;高鎭秀;明贊奎;閔聖基
    • 대한전자공학회논문지
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    • 제23권3호
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    • pp.384-388
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    • 1986
  • This paper describes the design and fabrication of an integrated circuit that can detect the teletext signal included in a composite video signal. The circuit that is based on the comparatorlevel sampling method can detect a stable data signal even from an external circuit with large variation. It has been fabricated by the SST bipolar standard process. Its chip size is $2.5x3.78mm^2$.

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옵셋전압을 저감시킨 실리콘 바이폴라 홀 IC 설계 (Design of HALL effect integrated circuit with reduced wolgate offset in silicon bipolar technology)

  • 김정언;홍창희
    • 전자공학회논문지A
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    • 제32A권1호
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    • pp.138-145
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    • 1995
  • The offset voltage in silicon Hall plates is mainly caused by stress and strain in package, and by alignment in process. The offset voltage is appeared random for condition change with time in the factory, is non-linearly changed with temperature. In this paper proposed new method of design of Hall IC, and methematicaly proved relation layout of chip of 90$^{\circ}$-shift-current Hall plate pair is matched with "Differentail to single ended Conversion amplifier." In the experiment, the offset voltage is reduced about 1/100 time than the original offset voltage.

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동기신호 분리용 집적회로의 설계 및 제거 (Design and Fabrication of SYNC Signal Separator IC)

  • 장영욱;김영생;갑명철
    • 대한전자공학회논문지
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    • 제24권6호
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    • pp.992-997
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    • 1987
  • This paper describes the design and fabrication of an integrated circuit that can separate the horizontal SYNC., vertical SYNC. and composite SYNC. signal included in a composite video signal. The circuit that is based on the comparator level samplign method can separate a stable SYNC. signal even from an external circuit with large variation. It has been fabrivated by the SST bipolar process. Its chip size is 1.5x1.5mm\ulcorner As a result, we succeeded in fabrication of IC which satisfied DC characteristics and SYNC. singal separator function.

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