• Journal of The Korean Society of Agricultural Engineers
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• v.59 no.1
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• pp.31-43
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• 2017

Recent studies about irrigation water use have focused on agricultural reservoir operation in irrigation period. At the same time, it is significant to store water resource in reservoir during non-irrigation period in order to secure sufficient water in early growing season. In this study, Representative Concentration Pathways (RCP) 4.5, 8.5 scenarios with the Global Climate Model (GCM) of The Second Generation Earth System Model (CanESM2) were downscaled with bias correlation method. Cumulative precipitation during non-irrigation season, October to March, was analyzed. Interaction between cumulative precipitation and carry-over storage was analyzed with linear regression model for ten study reservoirs. Using the regression model, reservoir drought response ability was evaluated with expression of excess and deficiency. The results showed that future droughts will be more severe than past droughts. Especially in case of non-exceedance probability of 10%, drought in southern region seemed to be serious. Nine study reservoirs showed deficiency range from 10% to 55%, which turned out to be vulnerable for future drought. Only Jang-Chan reservoir was secure for early growing season in spite of drought with deficiency of 8% and -2%. The results of this study represents current agricultural reservoirs have vulnerability for the upcoming drought.

• ETRI Journal
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• v.31 no.6
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• pp.660-666
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• 2009

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Zn-oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below $200^{\circ}C$, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as $Si_3N_4$ and $Al_2O_3$, the electrical properties are analyzed. After post-annealing at $200^{\circ}C$ for 1 hour in an $O_2$ ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a $Si_3N_4$ IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogen-based bonds. From constant-current stress tests of $I_d$ = 3 ${\mu}A$, an IGZO-TFT with heat-treated $Si_3N_4$ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.8
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• pp.42-47
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• 2000

Long-wavelength infrared (LWIR) detectors made of self-assembled quantum dots embedded in the channel region of high electron mobility transistor (HEMT) is demonstrated. Above 180 K, the detector shows low dark currents due to strong confinement effect of electrons in InAs quantum dots and exhibits the broad spectral response ranging from 7 mm to 11 mm. The peak detectivity ($D^*$) of $1.93{\times}10^{10}cmHz^{1/2}/W$ is obtained at 9.4 mm. The photocurrent characteristics as a function of applied bias are similar to that of normal FETs, while the photocurrent decreases as the applied electric field exceeds $2{\times}10^3V/cm$ because of the increased dark current.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.8
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• pp.62-67
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• 1999

In this letter, a scheme for increasing the input power dynamic range of wavelength converters based on cross-gain modulation (XGM) in semiconductor optical amplifiers (SOA/s) is proposed. We investigate the effect of input pump and probe powers on the power penalty, the measure of performance for the wavelength converters. As a result, we show that the optimal bit error rate (BER) performance can be obtained when the probe power is kept 3 dB weaker than the pump power. Using this characteristic, we propose the wavelength converter scheme that controls the probe power level by monitoring the input pump power and adjusting the bias current of probe source accordingly. Consequently, the wavelength converter for wide input power dynamic range can be implemented. We show that an input power dynamic range of more than 20 dB at 2.5 Gb/s is achievable.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.1-9
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• 2000

A new method, the external resistance method (ERM method), is proposed for accurate extraction of the gate bias-dependent effective channel carrier mobility (${\mu}_{eff}$) and separated parasitic source/drain resistances ($R_S$ and $R_D$) of n-channel MOSFET's. The proposed ERM method is applied to n-channel LDD MOSFETs with two different gate lengths ($W_m/L_m=30{\mu}m/0.6{\mu}m,\;30{\mu}m/1{\mu}m$) in the linear mode of current-voltage characteristics ($I_D-V_{GS},\;V_{DS}$). We also considered gate voltage dependence of separated $R_2$ and $R_D$ in the accurate modeling and extraction of effective channel carrier mobility. Good agreement of experimental data is observed in submicron n-channel LDD MOSFETs. Combining with capacitance-voltage characteristics, the ERM method is expected to be very useful for accurate and efficient extraction of ${\mu}_{eff},\;R_D,\;R_S$, and other characteristic parameters in both symmetric and asymmetric structure MOSFET's in which parasitic resistances are critical to the improvement of high speed performance and reliability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.274-286
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• 2016

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using $0.13-{\mu}m$ CMOS technology and the die area is $4.2mm^2$. The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

• Journal of Ecology and Environment
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• v.41 no.2
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• pp.34-44
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• 2017

Background: Monitoring terrestrial vegetation cover condition is important to evaluate its current condition and to identify potential vulnerabilities. Due to simplicity and low cost, point intercept method has been widely used in evaluating grassland surface and quantifying cover conditions. Field-based digital photography method is gaining popularity for the purpose of cover estimate, as it can reduce field time and enable additional analysis in the future. However, the caveats and uncertainty among field-based vegetation cover estimation methods is not well known, especially across a wide range of cover conditions. We compared cover estimates from point intercept and digital photography methods with varying sampling intensities (25, 49, and 100 points within an image), across 61 transects in typical steppe, forest steppe, and desert steppe in central Mongolia. We classified three photosynthetic groups of cover important to grassland ecosystem functioning: photosynthetic vegetation, non-photosynthetic vegetation, and bare soil. We also acquired normalized difference vegetation index from satellite image comparison with the field-based cover. Results: Photosynthetic vegetation estimates by point intercept method were correlated with normalized difference vegetation index, with improvement when non-photosynthetic vegetation was combined. For digital photography method, photosynthetic and non-photosynthetic vegetation estimates showed no correlation with normalized difference vegetation index, but combining of both showed moderate and significant correlation, which slightly increased with greater sampling intensity. Conclusions: Results imply that varying greenness is playing an important role in classification accuracy confusion. We suggest adopting measures to reduce observer bias and better distinguishing greenness levels in combination with multispectral indices to improve estimates on dry matter.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.3
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• pp.39-45
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• 1998

SrBi$_{2}$Ta$_{2}$O$_{9}$ (SBT) ferroelectric thin films for nonvolatile memory were prepared on Pt/Ti/SiO$_{2}$/Si and RuO$_{2}$/SiO$_{2}$/Si substrates by RF magnetron sputtering. The dependences of crystalline and electrical properties on the lower electrode type(Pt and RuO$_{2}$) and the annealing temperatures were investigated. SBT films regardless of their electrode types showed typeical Bi layered peroviskite crystal structures. The crystalline quality of as-deposited SBT films was improved by the rapid thermal annealing at 650.deg. C for 30 sec. The remanetn polarization of 2Pr (Pr+-Pr-) of the annealed SBT films deposited on Pt/Ti/SiO$_{2}$/Si substrates were about 11 .mu.C/cm$^{2}$ and 3 .mu.C/cm$^{2}$, respectively. The leakage currents at 3 V bias voltage were about 0.8 .mu.A/cm$^{2}$ for SBT/ Pt/Ti/SiO$_{2}$/Si and about 1 .mu.A/cm$^{2}$ for SBT/RuO$_{2}$/SiO$_{2}$/Si sample. SBT films annealed at 650 .deg. C showed no degradation in Pr values after 10$^{11}$ polarization switching cycles, indicating good fatigue properties. In addition, for SBT samples deposited on Pt/Ti/SiO$_{2}$/Si, Pr values increased to more than that of initial state, suggesting the increament of leakage current caused by repeated polarization.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1422-1428
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• 2014

This paper has analyzed threshold voltage roll-off for bottom gate voltages of asymmetric double gate(DG) MOSFET. Since the asymmetric DGMOSFET is four terminal device to be able to separately bias for top and bottom gates, the bottom gate voltage influences on threshold voltage. It is, therefore, investigated how the threshold voltage roll-off known as short channel effects is reduced with bottom gate voltage. In the pursuit of this purpose, off-current model is presented in the subthreshold region, and the threshold voltage roll-off is observed for channel length and thickness with a parameter of bottom gate voltage as threshold voltage is defined by top gate voltage that off-currnt is $10^{-7}A/{\mu}m$ per channel width. As a result to observe the threshold voltage roll-off for bottom gate voltage using this model, we know the bottom gate voltage greatly influences on threshold voltage roll-off voltages, especially in the region of short channel length and thickness.

• Journal of IKEEE
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• v.14 no.4
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• pp.257-262
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• 2010

We design a CMOS front-end with wide variable gain and low power consumption for 5.25 GHz band. To obtain wide variable gain range, a p-type metal-oxide-semiconductor field-effect transistor (PMOS FET) in the low noise amplifier (LNA) section is connected in parallel. For a mixer, single balanced and folded structure is employed for low power consumption. Using this structure, the bias currents of the transconductance and switching stages in the mixer can be separated without using current bleeding path. The proposed front-end has a maximum gain of 33.2 dB with a variable gain range of 17 dB. The noise figure and third-order input intercept point (IIP3) are 4.8 dB and -8.5 dBm, respectively. For this operation, the proposed front-end consumes 7.1 mW at high gain mode, and 2.6 mW at low gain mode. The simulation results are performed using Cadence RF spectre with the Taiwan Semiconductor Manufacturing Company (TSMC) $0.18\;{\mu}m$ CMOS technology.)