• 대한의생명과학회지
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• 제15권1호
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• pp.97-99
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• 2009

Geldanamycin is a benzoquinone ansamycin antibiotic that binds to cytosol HSP90 (Heat Shock Protein 90) and changes its biological function. HSP90 is involved in the intracellular important roles for the regulation of the cell cycle, cell growth, cell survival, apoptosis, angiogenesis and oncogenesis. To identify genes expressed during geldanamycin treatment against neurons of rats (PC12 cells), DNA microarray method was used. We have isolated 2 gene groups (up-or down-regulated genes) which are geldanamycin differentially expressed in neurons. Granzyme B is the gene most significantly increased among 204 up-regulated genes (more than 2 fold over-expression) and Chemokine (C-C motif) ligand 20 is the gene most dramatically decreased among 491 down-regulated genes (more than 2 fold down-expression). The gene increased expression of Cxc110, Cyp11a1, Gadd45a, Gja1, Gpx2, Ifua4, Inpp5e, Sox4, and Stip1 are involved stress-response gene, and Cryab, Dnaja1, Hspa1a, Hspa8, Hspca, Hspcb, Hspd1, Hspd1, and Hsph1 are strongly associated with protein folding. Cell cycle associated genes (Bc13, Brca2, Ccnf, Cdk2, Ddit3, Dusp6, E2f1, Illa, and Junb) and inflammatory response associated genes (Cc12, Cc120, Cxc12, Il23a, Nos2, Nppb, Tgfb1, Tlr2, and Tnt) are down-regulated more than 2 times by geldanamycin treatment. We found that geldanamycin is related to expression of many genes associated with stress response, protein folding, cell cycle, and inflammation by DNA microarray analysis. Further experimental molecular studies will be needed to figure out the exact biological function of various genes described above and the physiological change of neuronal cells by geldanamycin. The resulting data will give the one of the good clues for understanding of geldanamycin under molecular level in the neurons.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• 조명전기설비학회논문지
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• 제20권4호
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• pp.12-20
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• 2006

중화학 공업은 전해조를 포함한 비선형 부하를 가지고 있다. AC-DC 컨버터로 구성된 전해조는 고조파 전류를 발생시키고, 전력 계통의 전압을 왜곡 시킨다. 본 논문에서는 전해조 부하의 고조파 현장 측정, 고조파 저감을 위해 수용가 모선에 동조 필터 적용과 국제 고조파 관리 기준인 IEC 61000-3-6과 IEEE 519에 의한 고조파 평가를 심도있게 분석한다. 고조파 해석 프로그램인 EDSA는 사례연구에 시뮬레이션 도구로 사용되었다.

• Structural Engineering and Mechanics
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• 제25권5호
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• pp.565-576
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• 2007

The article describes a technique for the measurement of the level of complexity of fracture surfaces by the method of vertical sections, and a performed statistical analysis of the effect of profile lines on the fractographic and fractal parameters of fractures, i.e. the profile line development factor, $R_L$, and the fracture surface development factor, $R_S$, (as defined by the cycloid method), as well as the fractal dimension, $D_C$, (as determined by the chord method), and the fractal dimension, $D_{BC}$, (as determined by the box method). The above-mentioned parameters were determined for fracture surfaces of basalt and gravel concretes, respectively, which had previously been subjected to fracture toughness tests. The concretes were made from mixtures of a water/cement ratio ranging from 0.41 to 0.61 and with a variable fraction of coarse aggregate to fine aggregate, $C_{agg.}/F_{agg.}$, in the range from 1.5 to 3.5. Basalt and gravel aggregate of a fraction to maximum 16 mm were used to the tests. Based on the performed analysis it has been established that the necessary number of concrete fracture profile lines, which assures the reliability of obtained testing results, should amount to 12.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.465-468
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• 2004

In this paper, we describe the design and implementation of the new current-current negative feedback (CCNF) voltage-controlled oscillator (VCO), which suppresses 1/f induced low-frequency noise. By means of the CCNF, the high-frequency noise as well as the low-frequency noise is prevented from being converted into phase noise. The proposed CCNF VCO shows 11-dB reduction in phase noise at 10 kHz offset, compared with the conventional differential VCO. The phase noise of the proposed VCO is -87 dBc/Hz at 10 kHz offset frequency from 5.5-GHz carrier. The proposed VCO consumes 14.0 mA at 2.0 V supply voltage, and shows single-ended output power of -12.0 dBm.

• Journal of electromagnetic engineering and science
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• 제4권4호
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• pp.168-174
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• 2004

A bandwidth-enhanced and phase noise-improved differential LC-tank VCO is proposed in this paper. By connecting the varactors to the bases of the cross-coupled transistors of the proposed LC-tank VCO, its input negative resistance has been widened. Also, the feedback capacitor Cc in the cross-coupling path of the proposed LC-tank VCO attenuates the output common-mode level modulated by the low-frequency noise because the modulated common-mode level jitters the varactor bias point and degrades phase noise. Compared with the fabricated conventional LC-tank VCO, the proposed LC-tank VCO demonstrates $200\;\%$ enhancement in tuning range, and 6 - dB improvement in phase noise at 6 MHz offset frequency from 5.4-GHz carrier. We achieved the phase noise of - 106 dBc/Hz at 6 MHz offset, and $10\;\%$ tuning range from the proposed LC-tank VCO. The proposed LC-tank VCO consumes 12 mA at 2.5 V supply voltage.

• 한국항행학회논문지
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• 제12권1호
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• pp.28-33
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• 2008

인터넷 망을 사용하여 음성 서비스를 제공하는 VoIP는 초기의 호기심을 벗어나 이제는 사업의 한 아이템으로 각광 받고 있다. VoIP 기술은 인터넷을 통해 음성 데이터를 전달하는 기술로서 인터넷 전화 서비스가 기존 전화 서비스를 대체할 수 있어 이에 대한 관심이 커졌다. VoIP 기술은 기존 IP 기술을 이용하여 음성통신 서비스를 제공하기 때문에 IP 기반의 위협들을 그대로 상속하며, VoIP 서비스 제공을 위한 신규 기술들로 인해 발생하는 새로운 위협들을 가지고 있다. 따라서 본 논문에서는 VoIP 서비스의 보안위협에 대하여 살펴보고, 보안적용시의 문제점과 고려사항 및 대책에 대하여 제시하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.492-498
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• 2017

In this paper, we integrate a divide-by-3 injection-locked frequency divider (ILFD) in CMOS technology with a $0.18-{\mu}m$ BiCMOS process. We propose a self-injection technique that utilizes harmonic conversion to improve the locking range, phase-noise, and input sensitivity simultaneously. The proposed self-injection technique consists of an odd-to-even harmonic converter and a feedback amplifier. This technique offers the advantage of increasing the injection efficiency at even harmonics and thus realizes the low-power implementation of an odd-order division ILFD. The measurement results using the proposed self-injection technique show that the locking range is increased by 47.8% and the phase noise is reduced by 14.7 dBc/Hz at 1-MHz offset frequency with the injection power of -12 dBm. The designed divide-by-3 ILFD occupies $0.048mm^2$ with a power consumption of 18.2-mW from a 1.8-V power supply.

• 대한가정학회지
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• 제19권3호
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• pp.11-19
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• 1981

The purpose of this study were: (1) to ascertain the labels, (2) to investigate the designs and materials of blouses, and (3) to analyze the prices. The period of observation was from April 1st to May 10th, 1981. The interviews with related producers and saleswomen and a questionnaire were used for this study. The questionaire was made with items after finishing the pretest. The observation of six observers was made in markets(group D). B), commercial agents manufactures (group C), and bontiques group D). For the statistical analysis, 120 blouses were used among 154 blouses which were examined. The results of this study indicated that: (1) Blouses with labels were 56.7% by group A and 100.0% by group BC and D. (2) In the styles of blouses, box style was popular I four groups. (3) Among various types of sleeves, set-in sleeve was popular in four groups. The most sleeves were finished with cuffs. (4) The shirtwaist collars were popular in group AQ and B, rippled collars and chinese collars I group C, and rippled collars I group D.(5) In thee materials of blouses, polyester was poplar I group A and B, polyester/cotton in group C, and cotton in group d. (6) The prices of blouses were from 4,500 to 15,000 won in group A, from 5,000 to 37,300 won in group B, from 12,500 to 52,000 won in group C, and from 30,000 to 90,000 won in group D.

• Journal of electromagnetic engineering and science
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• 제9권2호
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.