• Title/Summary/Keyword: associative memory

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A Collaborative Recommendation Method based on Fuzzy Associative Memory (퍼지연상기억장치에 기반한 협력 추천 방법)

  • 이동섭;고일주;김계영
    • Journal of KIISE:Software and Applications
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    • v.31 no.8
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    • pp.1054-1061
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    • 2004
  • At recent, people can easily access to information by Internet to be rapidly evolving. And also, the amount is rapidly increasing. So the techniques, to automatically extract the required information are very important to reduce the time and the effort for retrieving information. In this paper, we describe a collaborative filtering system for automatically recommending high-quality information to users with similar interests on arbitrarily narrow information domains. It asks a user to rate a gauge set of items. It then evaluates the user's rates and suggests a recommendation set of items. We interpret the process of evaluation as an inference mechanism that maps a gauge set to a recommendation set. We accomplish the mapping with FAM (Fuzzy Associative Memory). We implemented the suggested system in a Web server and tested its performance in the domain of retrieval of technical papers, especially in the field of information technologies. The experimental results show that it may provide reliable recommendations.

A Model for diagnosing Students′Misconception using Fuzzy Cognitive Maps and Fuzzy Associative Memory (퍼지 인지 맵과 퍼지 연상 메모리를 이용한 오인진단 모델)

  • 신영숙
    • Korean Journal of Cognitive Science
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    • v.13 no.1
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    • pp.53-59
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    • 2002
  • This paper presents a model for diagnosing students'learning misconceptions in the domain of heat and temperature using fuzzy cognitive maps(FCM) and fuzzy associative memory(FAM). In a model for diagnosing learning misconceptions. an FCM can represent with cause and effect between preconceptions and misconceptions that students have about scientific phenomenon. An FAM which represents a neurallike memory for memorizing causal relationships is used to diagnose causes of misconceptions in learning. This study will present a new method for more autonomous and intelligent system than a model to diagnose misconceptions that was being done with classical methods in learning and may contribute as an intelligent tutoring system for learning diagnosis within various educational contexts.

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Memory retrieval with a DNA computing (DNA 연산을 이용한 기억 인출 시뮬레이션)

  • Kim Joon-Shik;Lee Eun-Seok;Noh Yung-Kyun;Zhang Byoung-Tak
    • Proceedings of the Korean Information Science Society Conference
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    • 2006.06a
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    • pp.34-36
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    • 2006
  • 본 연구는 특정 사물을 계속 접하면서 그 사물에 대한 기억 강도가 의식적 노력 없이도 점점 강화되는 암묵적 기억 인출과정 associative memory retrieval의 DNA 연산 가능성을 논한다. 예를 들어 한 표적 단어에 대한 노출이 이를 관찰하는 시스템에게 그 단어의 기억 강도를 강화시키는 반면, 그와 유사한 다른 단어는 천천히 감소되고 나머지 가장 다른 단어는 일찍 잊혀지는 현상을 생각할 수 있다. 이들 단어들과 알파벳 철자들을 DNA 염기서열로 표현하고 simulated annealing을 통하여 결합 결과를 얻는다. Ridge regression 형태의 supervised 학습을 통하여 한 가지 표적 단어가 많이 생성되도록 DNA 조각들의 개수 분포를 변화시켜 진행한다. 실험 예로 'tic' 'tac' 'toe' 세 가지 단어를 그 아이템으로 정하여 계속 자극받는 표적 단어의 갯수가 증가함을 DNA annealing 시뮬레이션을 통하여 확인할 수 있다. 또한 'tac' 과 't' 와 'c'를 공유하는 'tic' 의 감소 점도가 't'만을 공유하는 'toe' 보다 느림을 확인할 수 있다. 위의 실험들을 통해 연합기억associative memory의 암묵적 인출과정을 분자 층위에서 표현할 수 있음을 확인 할 수 있다.

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A Movement Instruction System Using Virtual Environment

  • Hatayama, Junichi;Murakoshi, Hideki;Yamaguchi, Toru
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2003.09a
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    • pp.70-73
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    • 2003
  • This paper proposes a movement instruction system using virtual environment. This system consists of a monitor, cameras, ana a PC. A learner is coached by a virtual instructor that is displayed in virtual environment as 3 dimensional computer graphics on the monitor. Virtual instructor shows sample movement and suggests mistakes of learner's movement by recognizing movement of learner's movement from the picture that cameras capture. To improve the robust characteristic of information from cameras, the system enables to select optimum inputs from cameras based on learner's movement It implemented by Fuzzy associative inference system Fuzzy associative inference system is implemented by bi-directional associative memory and fuzzy rules. It is suitable to convert obscure information into clear. We implement and evaluate the movement instruction system

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Development of the Hippocampal Learning Algorithm Using Associate Memory and Modulator of Neural Weight (연상기억과 뉴런 연결강도 모듈레이터를 이용한 해마 학습 알고리즘 개발)

  • Oh Sun-Moon;Kang Dae-Seong
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.43 no.4 s.310
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    • pp.37-45
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    • 2006
  • In this paper, we propose the development of MHLA(Modulatory Hippocampus Learning Algorithm) which remodel a principle of brain of hippocampus. Hippocampus takes charge auto-associative memory and controlling functions of long-term or short-term memory strengthening. We organize auto-associative memory based 3 steps system(DG, CA3, CAl) and improve speed of learning by addition of modulator to long-term memory learning. In hippocampal system, according to the 3 steps order, information applies statistical deviation on Dentate Gyrus region and is labelled to responsive pattern by adjustment of a good impression. In CA3 region, pattern is reorganized by auto-associative memory. In CAI region, convergence of connection weight which is used long-term memory is learned fast by neural networks which is applied modulator. To measure performance of MHLA, PCA(Principal Component Analysis) is applied to face images which are classified by pose, expression and picture quality. Next, we calculate feature vectors and learn by MHLA. Finally, we confirm cognitive rate. The results of experiments, we can compare a proposed method of other methods, and we can confirm that the proposed method is superior to the existing method.

AMN controller for dynamic control of robot manpulators (로봇 머니퓰레이터의 동력학 제어를 위한 AMN제어기)

  • 정재욱;국태용;이택종
    • 제어로봇시스템학회:학술대회논문집
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    • 1997.10a
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    • pp.1569-1572
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    • 1997
  • In this paper, we present an associative memory network (AMN) controller for dynamic robot control. The purpose of using AMN is to reduce the size of required memory in storing and recalling large of daa representing input relationship of nonlinear functions. With the capability AMN can be used to dynamic robot control, which has nonlinear properties inherently. The proposed AMN control scheme has advantages for the inverse dynamics learning no limitatiion of inpur range, and insensitive of payload change. Computer simulations show the effectiveness and feasibility of proposed scheme.

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Neural Circuit and Mechanism of Fear Conditioning (공포 조건화 학습의 신경회로와 기전)

  • Choi, Kwang-Yeon
    • Korean Journal of Biological Psychiatry
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    • v.18 no.2
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    • pp.80-89
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    • 2011
  • Pavlovian fear conditioning has been extensively studied for the understanding of neurobiological basis of memory and emotion. Pavlovian fear conditioning is an associative memory which forms when conditioned stimulus (CS) is paired with unconditioned stimulus (US) once or repeatedly. This behavioral model is also important for the understanding of anxiety disorders such as posttraumatic stress disorder. Here we describe the neural circuitry involved in fear conditioning and the molecular mechanisms underlying fear memory formation. During consolidation some memories fade out but other memories become stable and concrete. Emotion plays an important role in determining which memories will survive. Memory becomes unstable and editable again immediately after retrieval. It opens the possibility for us of modulating the established fear memory. It provides us with very efficient tools to improve the efficacy of cognitive-behavior therapy and other exposure-based therapy treating anxiety disorders.

신경 회로망 구현에서의 광연결

  • Lee, Hyeok
    • 전기의세계
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    • v.40 no.6
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    • pp.38-44
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    • 1991
  • 이 논문에서는 2장에서 신경회로망의 두가지 주요모델인 associative memory와 학습신경 회로망을 소개하고 특히 연결이 그의 중요한 요소임을 설명한다. 3장에서는 광 연결에 대한 구현으로서 spartial light modulator를 이용하는 방법과 체적 홀로그램을 사용하는 방법에 대해 구체적으로 기술한다. 4장에서는 결론으로서 광 연결을 이용한 신경회로망의 구현에 어떠한 문제가 있으며 앞으로 해결해야 할 점을 생각한다.

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Peducing the Overhead of Virtual Address Translation Process (가상주소 변환 과정에 대한 부담의 줄임)

  • U, Jong-Jeong
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.1
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    • pp.118-126
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    • 1996
  • Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.

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Design of an Asynchronous Data Cache with FIFO Buffer for Write Back Mode (Write Back 모드용 FIFO 버퍼 기능을 갖는 비동기식 데이터 캐시)

  • Park, Jong-Min;Kim, Seok-Man;Oh, Myeong-Hoon;Cho, Kyoung-Rok
    • The Journal of the Korea Contents Association
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    • v.10 no.6
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    • pp.72-79
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    • 2010
  • In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.