• Journal of Communications and Networks
• /
• v.13 no.1
• /
• pp.1-5
• /
• 2011

Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.86-93
• /
• 2008

The multi-mode terminal modem which is capable of accommodating a variety of wireless communication standards needs versatile arithmetic units for processing a variety of word lengths and wide range of data rates. Since the target hardware is usually designed to meet the required highest performance, it is often wasteful in power consumption especially when low rate data processing cases. Thus, a speed and power adaptability of the arithmetic unit is a desirable feature for the wireless applications. In this paper, we propose a power efficient versatile adder architecture with carry skip logic as a basic building block constructed in hierarchical manner. The validity of the architecture is shown with respect to size, performance, and power efficiency in diverse operating modes.

• Communications of the Korean Institute of Information Scientists and Engineers
• /
• v.1 no.1
• /
• pp.75-79
• /
• 1983

現代 컴퓨터의 연산장치(Arithmetic unit)의 design을 하는데 있어서 가장 중요하게 요구점점되는 點은 계산의 속도(Computational speed)와 計算의 정확성 (Computational accuracy)이라고 보겠다. 여기서는 정보처리기(Information processor)로서 또는 非數理的인 연산(Non-numeric operation)을 위한 도구로서 보다는 數理的 연산(Arithmetic)을 수행하는 도구로서의 컴퓨터 연산에 限해서만 論하고자 한다. 대개의 경우 기계를 고안하는 사람들은 계사의 속도에 對해서는 특별한 관심을 갖고 그러한 목적에 맞는 기계를 만들어 낼려고 하지만 數値의 정 확성(Numerical accuracy)에 對해서ㅡ 등한시했던 경우가 많았다고 보겠다. 그러 나 이 두 條件 즉 빠른 속도 틀림없는 정확성을 同時에 충족 시키고자 하는 것이 기계 고안자들의 理想 목포가 되는 것은 사시링다. 여기에 수반도는 문제는 제작 비를 고려하지 않을 수 없다는 것이다. 정화하고 빠른 operation을 할 수 있는 기 계는 너무 비싼 제작비가 들기 때문에 사용목적에 적절하게 두 문제를 절충하여 고려하는 것이 일반적이라 하겠다. 初期의 컴퓨터는 한 Word(Computer Word)로 서 36개의 bit를 사용한 것이 많았다고 본다. 그러나 1961년 4月 Tennessee에서 Oak Riage National Laboratory와 The Society for Industril and Applied Mathematics 후원하에 일주일에 걸친 국제회의가 열렸었는데 거기 모인 거의 모 든 學者들이 앞으로의 과학 연구용 컴퓨터(Scientific Computer)의 한 Word의 길 이는 적어도 48bit 이상으로 증가시켜야 된다는데 의견을 모았었다고 한다. 이제 rounding error의 성향(begavior)을 알아보기 위한 간단한 例를 들어 봄으로써 이 글을 쓰는 동기으 일면을 대신하고자 한다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.1
• /
• pp.88-95
• /
• 2002

In recent years, the security of hardware and software systems is one of the most essential factor of our safe network community. As elliptic Curve Cryptosystems proposed by N. Koblitz and V. Miller independently in 1985, require fewer bits for the same security as the existing cryptosystems, for example RSA, there is a net reduction in cost size, and time. In this thesis, we propose an efficient hardware architecture of underlying field arithmetic processor for Elliptic Curve Cryptosystems, and a very useful method for implementing the architecture, especially multiplicative inverse operator over GF$GF (2^m)$ onto FPGA and futhermore VLSI, where the method is based on optimized unit operation components. We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed We optimize the arithmetic processor for speed so that it has a resonable number of gates to implement. The proposed architecture could be applied to any finite field $F_{2m}$. According to the simulation result, though the number of gates are increased by a factor of 8.8, the multiplication speed and inversion speed has been improved 150 times, 480 times respectively compared with the thesis presented by Sarwono Sutikno et al. [7]. The designed underlying arithmetic processor can be also applied for implementing other crypto-processor and various finite field applications.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.5 no.3
• /
• pp.517-524
• /
• 2001

This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.11
• /
• pp.62-71
• /
• 2002

This paper presents new DSP (Digital Signal Processor) instructions and their hardware architecture for high-speed FFT. the instructions perform new operation flows, which are different from the MAC (Multiply and Accumulate) operation on which existing DSP chips heavily depend. The proposed DPU (Data Processing Unit) supporting the instructions shows two times faster than existing DSP chips for FFT. The architecture has been modeled by the Verilog HDL and logic synthesis has been performed using the 0.35 ${\mu}m$ standard cell library. The maximum operating clock frequency is about 144.5 MHz.

• Proceedings of the Korea Water Resources Association Conference
• /
• 2021.06a
• /
• pp.287-287
• /
• 2021

본 연구에서는 CUDA(Compute Unified Device Architecture) 포트란을 이용하여 확산파 강우 유출모형을 개발하였다. CUDA 포트란은 그래픽 처리 장치(Graphic Processing Unit: GPU)에서 수행하는 병렬 연산 알고리즘을 포트란 언어를 사용하여 작성할 수 있도록 하는 GPU상의 범용계산(General-Purpose Computing on Graphics Processing Units: GPGPU) 기술이다. GPU는 그래픽 처리 작업에 특화된 다수의 산술 논리 장치(Arithmetic Logic Unit: ALU)로 구성되어 있어서 중앙 처리 장치(Central Processing Unit: CPU)보다 한 번에 더 많은 연산 수행이 가능하다. 이에 따라, CUDA 포트란기반 확산파모형은 분포형 강우유출모형의 수치모의 연산시간을 단축시킬 수 있다. 분포형모형의 지배방정식은 확산파모형과 Green-Ampt모형으로 구성되었고, 확산파모형은 유한체적법을 이용하여 이산화 하였다. CUDA 포트란기반 확산파모형의 정확성은 기존 연구된 수리실험 결과 및 CPU기반 강우유출모형과 비교하였으며, 연산소요시간에 대한 효율성은 CPU기반 확산파모형과 비교하였다. 그 결과 CUDA 포트란기반 확산파모형의 결과는 수리실험 결과 및 CPU기반 강우유출모형의 결과와 유사한 결과를 나타냈다. 또한, 연산소요시간은 CPU 기반 확산파모형의 연산소요시간보다 단축되었으며, 본 연구에 사용된 장비를 기준으로 최대 100배 정도 단축되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.12
• /
• pp.79-90
• /
• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.12
• /
• pp.2714-2726
• /
• 1997

In this paper, adaptive symbol changes-based medical image compression method is presented. First, the differenctial image domain is obtained using the differentiation rules or obaptive predictors applied to original mdeical image. Also, the algorithm determines the context associated with the differential image from the domain. Then prediction symbols which are thought tobe the most probable differential image values are maintained at a high value through the adaptive symbol changes procedure based on estimates of the symbols with polarity coincidence between the differential image values to be coded under to context and differential image values in the model template. At the coding step, the differential image values are encoded as "predicted" or "non-predicted" by the binary adaptive arithmetic encoder, where a binary decision tree is employed. The simlation results indicate that the prediction hit ratios of differential image values using the proposed algorithm improve the coding gain by 25% and 23% than arithmetic coder with ISO JPEG lossless predictor and arithmetic coder with differentiation rules or adaptive predictors, respectively. It can be used in compression part of medical PACS because the proposed method allows the encoder be directly applied to the full bit-planes medical image without a decomposition of the full bit-plane into a series of binary bit-planes as well as lower complexity of encoder through using an additions when sub-dividing recursively unit intervals.

• School Mathematics
• /
• v.14 no.2
• /
• pp.191-212
• /
• 2012

In the field of arithmetic in mathematics education, there has been lack of fine-grained investigations addressing the relationship between students' construction of division knowledge with fractional quantities and their whole number division knowledge. This study, through the analysis of part of collected data from a year-long teaching experiment, presents a possible constructive itinerary as to how a student could modify her unit-segmenting scheme to deal with various fraction measurement division situations: 1) unit-segmenting scheme with a remainder, 2) fractional unit-segmenting scheme. Thus, this study provides a clue for curing a fragmentary approach to teaching whole number division and fraction division and preventing students' fragmentary understanding of the same arithmetical operation in different number systems.