• Title/Summary/Keyword: arithmetic unit

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Hardware Architecture of High Performance Cipher for Security of Digital Hologram (디지털 홀로그램의 보안을 위한 고성능 암호화기의 하드웨어 구조)

  • Seo, Young-Ho;Yoo, Ji-Sang;Kim, Dong-Wook
    • Journal of Broadcast Engineering
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    • v.17 no.2
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    • pp.374-387
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    • 2012
  • In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.

Extraction of the ship movement information by a radar target extractor (Radar Target Extractor에 의한 선박운동정보의 추출에 관한 연구)

  • Lee, Dae-Jae;Kim, Kwang-Sik;Byun, Duck-Soo
    • Journal of the Korean Society of Fisheries and Ocean Technology
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    • v.38 no.3
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    • pp.249-255
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    • 2002
  • This paper describes on the extraction of ship's real-time movement information using a combination full-function ARPA radar and ECS system that displays radar images and an electronic chart together on a single PC screen. The radar target extractor(RTX) board, developed by Marine Electronics Corporation of Korea, receives radar video, trigger, antenna bearing pulse and heading pulse signals from a radar unit and processes these signals to extract target information. The target data extracted from each pulse repetition interval in DSPs of RTX that installed in 16 bit ISA slot of a IBM PC compatible computer is formatted into a series of radar target messages. These messages are then transmitted to the host PC and displayed on a single screen. The position data of target in range and azimuth direction are stored and used for determining the center of the distributed target by arithmetic averaging after the detection of the target end. In this system, the electronic chart or radar screens can be displayed separately or simulaneously and in radar mode all information of radar targets can be recorded and replayed In spite of a PC based radar system, all essential information required for safe and efficient navigation of ship can be provided.

FPGA Implementation of a Grant Distribution Algorithm for the MAC in the ATM-PON (ATM-PON에서 MAC을 위한 승인분배 알고리즘의 FPGA 구현)

  • Kim, Tae-Min;Chung, Hae;Shin, Gun-Soon;Kim, Jin-Hee
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.38 no.10
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    • pp.1-9
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    • 2001
  • The MAC (Medium Access Control) protocol is needed for the OLT(Optical Line Termination) to allocate bandwidth to ONUs(Optical Network Units) and ONTs(Optical Network Terminations) dynamically in the ATM PON(Passive Optical Network). With the protocol, the OLT gathers ONUs' informations and provides grants efficiently to each ONU. Two important functions of the MAC protocol is the grant request procedure and the grant distribution algrithm. The latter has the greatest arithmetic portion in the TC(Transmission Convergence) module, occupies a relatively large portion of the overall chip area, has often been the limiting factor in terms of speed, and should be designed to guarantee the quality of service for various traffics. In this paper, we implement the MAC with the FPGA which can allocate grants dynamically according to the queue length information and the number of active ONUs and distribute grants uniformly to minimize the cell delay variation for each ONU. The structure of the MAC scheduler for the dynamic bandwidth assignment has a programmable look-up table. Also, it has a simple structure, the less chip area, and the lower delay time.

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Development of Stem Analysis Program(Stemwin1.0) for Windows (Windows용 수간석해(樹幹析解) 프로그램(Stemwin1.0)의 개발(開發))

  • Lee, Joon-Hak;Lee, Woo-Kyun;Seo, Jeong-Ho
    • Journal of Korean Society of Forest Science
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    • v.90 no.3
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    • pp.331-337
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    • 2001
  • This study was performed to develope stem analysis program(Stemwin1.0) which can be used in PC with MS-Windows operating system. Stemwin1.0 uses width of annual tree ring measured with 1/100mm unit, and calculate increments of several growth factors such as DBH, height and volume with various methods. Mean DBH can be calculated by arithmetic and quadratic mean methods. Height can be estimated by parallel line, line extending and height curve methods. Volume can be estimated by Huber, Smalian, and Spline functions. Not only Total growth, Mean Annual Increment(MAI) and Current Annual Increment(CAI) of growth factors, but also merchantable volume and height, form factor, growth rate, and merchantable volume rate are automatically calculated. Stemwin1.0 can also output accurate stem taper curve with various scale, and prepare stem taper data(diameter at different disk heights) for statistical analysis for deriving stem taper model. Stemwin1.0 can export output data and graph to Excel for more compatible use of it.

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A New Optical Access Network Structure for the convergence of Broadcast and Communication (방송통신 통합을 위한 새로운 광가입자망 구조에 관한 연구)

  • Hur Jung;Koo Bon-Jeong;Hyun Jae-Myoung;Park Youngil
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • 2004.11a
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    • pp.17-20
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    • 2004
  • 가정 내에 방송과 총신을 통합하여 제공하기 위한 방법으로서 수동광가입자망(Passive Optical Network)이 제안되고 있다 이를 구현하기 위해 여러 방식들이 연구되고 있는데 크게는 방송과 통신에 각기 다른 파장을 이용하는 방식과, 이들을 시간 다중화 하여 한 개의 과장으로 송신하는 방식으로 나눌 수 있다. 또한 동신에 이용하는 과장의 경우 각 가입자에게 다른 파장을 적용하는 WPON 방식과 모든 가입자에게 한 개의 파장만을 이용하되 시간영역에서 다중화하고 이터넷 프로토콜을 적용하는 EPON 방식으로 구분할 수 있다. WPON의 경우 EPON에 비해 수월하게 광대역 서비스를 할 수 있는 장점이 있으나, 각 가입자 과장의 제어 및 관리가 복잡하며, 고비용을 요구한다. 반면 EPON의 경우 채널의 효율성은 극대화할 수 있으나, 동시 이용자가 많을 경우 전송 속도가 하락한다. 한편, 방송과 통신을 통합한 채널의 특성을 살펴보면 가입자 방향으로의 하향 신호의 양이 중양국 방향으로의 상향 신호의 양에 비해 훨씬 많은 비대칭 구조이다. 따라서 본 연구에서는 이러한 채널 특성에 맞도록 하향 전송에는 WPON의 구조를 이용하고, 상향 전송에는 EPON의 구조를 적용하는 새로운 구조의 광가입자망을 제안하였다. 제안된 구조에 적합한 MPCP (Multi-Point Control Protocol) 프로토콜을 제시하고, 가입자 장치의 여러 종속 신호를 다중화하고 전송할 수 있는 ONU (Optical Network Unit)의 구조를 제안하였다. 또한 이러한 구조를 갖는 W-EPON 테스트베드를 구현하고 전송 시험을 통해 제시된 구조의 적합성을 측정한 결과를 보인다.4 Textual format) 파일을 생성한다. 또한, 콘텐츠 전송 및 저장의 효율성을 위해 이진 포멧인 IPMP화된 MP4 파일을 생성할 수 있다.으로써, 에러 이미지가 가지고 있는 엔트로피에 좀 근접하게 코딩을 할 수 있게 되었다. 이 방법은 실제로 Arithmetic Coder를 이용하는 다른 압축 방법에 그리고 적용할 수 있다. 실험 결과 압축효율은 JPEG-LS보다 약 $5\%$의 압축 성능 개선이 있었으며, CALIC과는 대등한 압축률을 보이며, 부호화/복호화 속도는 CALIC보다 우수한 것으로 나타났다.우 $23.87\%$($18.00\~30.91\%$), 갑폭 $23.99\%$($17.82\~30.48\%$), 체중 $91.51\%$($58.86\~129.14\%$)이였으며 성장율은 사육 온도구간별 차는 없었다.20 km 까지의 지점들(지점 2에서 지점 6)에서 매우 높은 값을 보이며 이는 조석작용으로 해수와 담수가 강제혼합되면서 표층퇴적물이 재부유하기 때문이라고 판단된다. 영양염류는 월별로 다소의 차이는 있으나, 대체적으로 지점 1과 2에서 가장 낮고, 상류로 갈수록 점차 증가하며 지점 7 상류역이 하류역에 비해 높은 농도이다. 월별로는 7월에 규산염, 용존무기태질소 및 암모니아의 농도가 가장 높은 반면에 용존산소포화도는 가장 낮다. 그러나 지점 14 상류역에서는 5월에 측정한 용존무기태질소, 암모니아, 인산염 및 COD 값이 7월보다 다소 높거나 비슷하다. 한편 영양염류와 COD값은 대체적으로 8월에 가장 낮으나

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Design of a Low Power Digital Filter Using Variable Canonic Signed Digit Coefficients (가변 CSD 계수를 이용한 저전력 디지털 필터의 설계)

  • Kim, Yeong-U;Yu, Jae-Taek;Kim, Su-Won
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.7
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    • pp.455-463
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    • 2001
  • In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

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A Parallel Processing Technique for Large Spatial Data (대용량 공간 데이터를 위한 병렬 처리 기법)

  • Park, Seunghyun;Oh, Byoung-Woo
    • Spatial Information Research
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    • v.23 no.2
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    • pp.1-9
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    • 2015
  • Graphical processing unit (GPU) contains many arithmetic logic units (ALUs). Because many ALUs can be exploited to process parallel processing, GPU provides efficient data processing. The spatial data require many geographic coordinates to represent the shape of them in a map. The coordinates are usually stored as geodetic longitude and latitude. To display a map in 2-dimensional Cartesian coordinate system, the geodetic longitude and latitude should be converted to the Universal Transverse Mercator (UTM) coordinate system. The conversion to the other coordinate system and the rendering process to represent the converted coordinates to screen use complex floating-point computations. In this paper, we propose a parallel processing technique that processes the conversion and the rendering using the GPU to improve the performance. Large spatial data is stored in the disk on files. To process the large amount of spatial data efficiently, we propose a technique that merges the spatial data files to a large file and access the file with the method of memory mapped file. We implement the proposed technique and perform the experiment with the 747,302,971 points of the TIGER/Line spatial data. The result of the experiment is that the conversion time for the coordinate systems with the GPU is 30.16 times faster than the CPU only method and the rendering time is 80.40 times faster than the CPU.