• Proceedings of the Korean Institute Of Construction Engineering and Management
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• 2006.11a
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• pp.435-439
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• 2006

The purposes of study is to propose a new method contract price adjustment in construction projects. The research method of this study includes a case analysis and questionnaire survey. The results of this study are as follows: 1) For improvement method of contract amount adjustment, enactment for legislation pertaining to computation methods such as military's organization through total unit cost, and price flexibility computation at the point of design modification were presented. 2) Arithmetic formulas for cases in which volume is deleted or modified below the price flexibility exemption amount or in which there is no change to quantity, at the occurrence of design modification resulting from price flexibility, were proposed.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.6
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• pp.1027-1034
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• 2017

In this paper, we propose a new function embedding method that can measure mathematical projections of probability amplitude, probability, average expectation and matrix elements of stationary-state unit matrix at all control operation points of quantum gates. The function embedding method in this paper is to embed orthogonal normalization condition of probability amplitude for each control operating point into a binary scalar operator by using Dirac symbol and Kronecker delta symbol. Such a function embedding method is a very effective means of controlling the arithmetic power function of a unitary gate in a unitary transformation which expresses a quantum gate function as a tensor product of a single quantum. We present the results of evolutionary operation and projective measurement when we apply the proposed function embedding method to the ternary 2-qutrit cNOT gate and compare it with the existing methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.101-108
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• 2004

A 16-bit adiabatic ALU(arithmetic logic unit) is designed. A simplified four-phase clock generator is also designed to provide supply clocks for the adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on ECRL (efficient charge recovery logic) using a 0.35${\mu}{\textrm}{m}$ CMOS technology. The post-layout simulation results show that the power consumption of the adiabatic ALU including supply clock generator is reduced by a factor of 1.15-1.77 compared to the conventional CMOS ALU with the same structure.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1491-1497
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• 2004

The psychoacoustic model in MPEG audio layer-III (MP3) encoder is optimized for the fixed-point processing. The optimization process consists of determining the data word length of arithmetic unit and the algorithm for transcendental functions that are often used in the psychoacoustic model. In order to determine the data word length, we defined a statistical model expressing the relation between the fixed-point operation errors of the psychoacoustic model and the probability of alteration of the allocated bits doe to these errors. Based on the simulations using this model, we chose a 24-bit data path and constructed a 24-bit fixed-point MP3 encoder. Sound quality tests using the constructed fixed-point encoder showed a mean degradation of -0.2 on ITU-R 5-point audio impairment scale.

• The KIPS Transactions:PartA
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• v.14A no.4
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• pp.203-208
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• 2007

This paper proposes a $64{\times}64$ Modified Booth multiplier using CMOS multi-valued logic circuits. The multiplier based on the radix-4 algorithm is designed with current mode CMOS quaternary logic circuits. Designed multiplier is reduced the transistor count by 64.4% compared with the voltage mode binary multiplier. The multiplier is designed with Samsung $0.35{\mu}m$ standard CMOS process at a 3.3V supply voltage and unit current $5{\mu}m$. The validity and effectiveness are verified through the HSPICE simulation. The voltage mode binary multiplier is achieved the occupied area of $7.5{\times}9.4mm^2$, the maximum propagation delay time of 9.8ns and the average power consumption of 45.2mW. This multiplier is achieved the maximum propagation delay time of 11.9ns and the average power consumption of 49.7mW. The designed multiplier is reduced the occupied area by 42.5% compared with the voltage mode binary multiplier.

• The Mathematical Education
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• v.40 no.2
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• pp.195-215
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• 2001

The purpose of this paper is to present a specific set of home teaching methods in hopes to prevent slow learner of the elementary mathematics. This paper deals with the number and operations, one of five topics in the elementary mathematics A survey of two hundred elementary school teachers was made to see the teacher's opinions of the role of home studying and to concretize the contents of the research topics. There were asked which is the most essential contents for the concrete loaming and which is the most difficult monad that might cause slow leaner. And those were found to be; counting, and arithmetic operations(addition and subtraction) of one or two-digit numbers and multiplication and their concepts representations and operations(addition and subtraction) of fractions. The home teaching methods are based on the situated learning about problem solving in real life situations and on the active teaming which induces children's participation in the process of teaching and learning. Those activities in teaching each contents are designed to deal with real objects and situations. Most teaching methods are presented in the order of school curriculum. To teach the concepts of numbers and the place value, useful activities using manipulative materials (Base ten blocks, Unifix, etc.) or real objects are also proposed. Natural number's operations such as addition, subtraction and multiplication are subdivided into small steps depending upon current curriculum, then for understanding of operational meaning and generalization, games and activities related to the calculation of changes are suggested. For fractions, this paper suggest 10 learning steps, say equivalent partition, fractional pattern, fractional size, relationship between the mixed fractions and the improper fraction, identifying fractions on the number line, 1 as a unit, discrete view point of fractions, comparison of fractional sizes, addition and subtraction, quantitative concepts. This research basically centers on the informal activities of kids under the real-life situation because such experiences are believed to be useful to prevent slow learner. All activities and learnings in this paper assume children's active participation and we believe that such active and informal learning would be more effective for learning transfer and generalization.

• Journal of IKEEE
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• v.25 no.1
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• pp.88-94
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• 2021

Public-key cryptographic algorithms such as RSA and ECC, which are currently in use, have used mathematical problems that would take a long time to calculate with current computers for encryption. But those algorithms can be easily broken by the Shor algorithm using the quantum computer. Lattice-based cryptography is proposed as new public-key encryption for the post-quantum era. This cryptographic algorithm is performed in the Polynomial Ring, and polynomial multiplication requires the most processing time. Therefore, a hardware model module is needed to calculate polynomial multiplication faster. Number Theoretic Transform, which called NTT, is the FFT performed in the finite field. The logic verification was performed using HDL, and the proposed design at the transistor level using Hspice was compared and analyzed to see how much improvement in delay time and power consumption was achieved. In the proposed design, the average delay was improved by 30% and the power consumption was reduced by more than 8%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.71-76
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• 2008

H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.

• Journal of Korean Society of Environmental Engineers
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• v.29 no.3
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• pp.277-282
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• 2007

For more accurate and practical design of the residual treatment train at water treatment plants(WTPs), a computational program based on the commercial spreadsheet, Microsoft Excel, was developed. The computational program for the design of a residual treatment train(DRTT) works in three steps which estimate the residual production to be treated, analyze the mass balance, and determine the size of each unit process. Of particular interest in the DRTT program, is provision for a filter backwash recycle system consisting of surge tank and sedimentation basin for more efficient recycling of backwash water. When the DRTT program was applied to the Chungju WTP, the program was very beneficial in avoiding errors which might have occurred during arithmetic calculations and in reducing the time needed to get the output. It is anticipated that the DRTT program could be used for design of new WTPs as well as the rehabilitation of existing ones.