Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Design and Implementation of 16-bit Adiabatic ALU for Micro-Power Processor

초저전력 프로세서용 16-bit 단열 ALU의 설계 및 구현

  • Lee, Han-Seung (Dept. of Electronics Engineering, Soongsil University) ;
  • Na, In-Ho (Dept. of Electronics Engineering, Soongsil University) ;
  • Moon, Yong (School of Electronic Engineering, Soongsil University) ;
  • Lee, Chan-Ho (School of Electronic Engineering, Soongsil University)
  • 이한승 (숭실대학교 전자공학과) ;
  • 나인호 (숭실대학교 전자공학과) ;
  • 문용 (숭실대학교 정보통신전자공학부) ;
  • 이찬호 (숭실대학교 정보통신전자공학부)
  • Published : 2004.05.01
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Abstract

A 16-bit adiabatic ALU(arithmetic logic unit) is designed. A simplified four-phase clock generator is also designed to provide supply clocks for the adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on ECRL (efficient charge recovery logic) using a 0.35${\mu}{\textrm}{m}$ CMOS technology. The post-layout simulation results show that the power consumption of the adiabatic ALU including supply clock generator is reduced by a factor of 1.15-1.77 compared to the conventional CMOS ALU with the same structure.

단열회로를 이용하여 16-bit ALU와 단열회로에 4가지 위상을 가지는 전원클럭을 공급하기 위한 전원클럭 발생기를 설계하였다. 4개의 전원클럭 신호선의 전하는 AC 형태의 전원클럭을 통해서 복원되어 에너지 소모를 줄인다. 구현에 사용한 단열회로는 ECRL(efficient charge recovery logic) 형태를 기본으로 하였으며 0.35㎛ CMOS 공정을 사용하여 설계하였고 3.3V 전원을 사용하였다. 회로설계 후 layout을 진행하였으며, layout 후 LPE(layout parasitic extraction)를 수행하여 이를 모의실험에 사용하였다. 모의실험결과 전원클럭 발생기를 포함한 단열회로를 이용한 ALU는 동일한 구조를 갖는 기존의 CMOS ALU보다 1.15～1.77배 정도의 에너지소모를 감소 시켰다.

Keywords

References

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