• East Asian mathematical journal
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• 제31권2호
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• pp.211-244
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• 2015

The arithmetic operation have double-sided character. One is calculation as a process, the other is understanding in results as an outcome of the operation. We harbored suspicion on students' misunderstanding in an outcome of the operation, because the curriculum has focused on the calculation, as a process of arithmetic operation. This study starts with the presentation of this problem, we tried to find the recognition ability and character in the arithmetic operation. We researched the recognition ability for 7th grade 27 students who have enough experience in arithmetic operation when studying in elementary school. And we had an interview with 3students individually, that has an error in understanding in results of arithmetic operation but has no error in calculation. We focused on 3students' detailed appearance of the ability to understand in results of arithmetic operation and analysed the changing appearance after recommending unit record using operation expression. As a result, we could find the abily to underatanding in results of arithmetic operation and applicability to recommend unit record using operation expression. Through these results, we suggested educational implications in understanding in results of arithmetic operation.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.1023-1024
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• 2015

본 논문에서는 Galois체에 기초를 둔 고효율 산술연산기 구성에 관한 한가지 방법을 제안하였다. 제안한 연산기는 기존의 방법에 비해 좀 더 규칙적이고 확장성이 용이한 이점이 있으며, 또한, 각종 멀티미디어 하드웨어 구성시의 기본인 연산기로 적용 및 응용할 수 있다. 향 후 연구과제로는 좀 더 콤팩트하고 효과적인 산술연산 알고리즘의 도출이 필요하며, 이에 논리연산기를 접목하여 산술연산 및 논리연산을 수행하는 연산전용 프로세서의 개발이 필요하다.

• 한국통신학회논문지
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• 제21권5호
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Journal of information and communication convergence engineering
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• 제9권4호
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• pp.435-440
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• 2011

This paper propose the method of constructing the highly efficiency adder and multiplier systems over finite fields. The addition arithmetic operation over finite field is simple comparatively because that addition arithmetic operation is analyzed by each digit modP summation independently. But in case of multiplication arithmetic operation, we generate maximum k=2m-2 degree of ${\alpha}^k$ terms, therefore we decrease k into m-1 degree using irreducible primitive polynomial. We propose two method of control signal generation for the purpose of performing above decrease process. One method is the combinational logic expression and the other method is universal signal generation. The proposed method of constructing the highly adder/multiplier systems is as following. First of all, we obtain algorithms for addition and multiplication arithmetic operation based on the mathematical properties over finite fields, next we construct basic cell of A-cell and M-cell using T-gate and modP cyclic gate. Finally we construct adder module and multiplier module over finite fields after synthesizing ${\alpha}^k$ generation module and control signal CSt generation module with A-cell and M-cell. Next, we constructing the arithmetic operation unit over finite fields. Then, we propose the future research and prospects.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.715-718
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• 2005

Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.

• 한국정보통신학회논문지
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• 제16권4호
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• pp.771-777
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• 2012

본 논문에서는 공통 연산기(Common Operation Unit)를 이용한 CABAC의 이진 산술 부호화기를 제안한다. 제안한 공통 연산기는 모드에 상관없이 하나의 공통 연산기를 이용하여 산술 부호화 및 재정규화를 수행하는 이진 산술 부호화기의 하드웨어 구조를 단순하게 구현할 수 있다. 제안하는 CABAC의 이진 산술 부호화기는 Context RAM, Context Updater, Common Operation Unit, Bit-Gen으로 구성되며 매 클럭당 하나의 심볼이 부호화될 수 있는 4단 파이프라인으로 구성하였다. 제안한 CABAC의 이진 산술 부호화기는 기존 CABAC의 이진 산술 부호화기와 비교하여 게이트 수는 최대 47% 감소하였고, 동작 주파수는 최대 19% 성능이 향상됨을 확인하였다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.856-859
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• 2005

본 논문에서는 Galois체에 기초를 둔 고효율 산술연산기 구성에 관한 한가지 방법을 제안하였다. 제안한 연산기는 기존의 방법에 비해 좀 더 규칙적이고 확장성이 용이한 이점이 있으며, 또한, 각종 멀티미디어 하드웨어 구성시의 기본인 연산기로 적용 및 응용할 수 있다. 향 후 연구과제로는 좀 더 콤팩트하고 효과적인 산술연산 알고리즘의 도출이 필요하며, 이에 논리 연산기를 접목하여 산술연산 및 논리연산을 수행하는 연산전용 프로세서의 개발이 필요하다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2000년도 춘계학술대회 학술발표 논문집
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• pp.5-8
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• 2000

Using the concept of a piecewise linear function, we present new operations for fuzzy arithmetic and then compare the operation based by the extension principle with the new operation.

• 대한전자공학회논문지
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• 제25권5호
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.